Semiconductor Device Minimizing Loop Area for Parasitic Reduction
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Solution Overview
Problem
Semiconductor devices with normally-on field-effect transistors, such as AlGaN/GaN HFETs, face limitations due to parasitic parameters of the package, leading to increased power loss and reduced switching speed, as the inherent electrical characteristics are influenced by capacitance, resistance, and inductance of the package, causing ringing and electric current leakage during switching.
Innovation Solution
A semiconductor device configuration with a normally-on and a normally-off switching active element cascode-connected on an electrically conductive substrate, where the source and drain electrode pads are positioned in proximity to minimize the loop area, reducing parasitic parameters' influence by optimizing the electric current path's inductance and resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the first source electrode pad and the second drain electrode pad are positioned far apart, then the mounting and connection precision tolerances are easier to accommodate, but the loop area increases causing increased parasitic inductance and resistance
Solution Approach 1:
The patent optimizes the spatial parameters (positioning) of the first source electrode pad and second drain electrode pad to achieve a minimum distance configuration. This parameter optimization reduces the loop area to minimal dimensions while remaining within manufacturing tolerance limits, thereby minimizing parasitic inductance and resistance without compromising mounting feasibility
Solution Approach 2:
The patent applies local quality optimization by specifically minimizing the loop area between the first source electrode pad and second drain electrode pad, while other parts of the device maintain their functional requirements. This localized optimization of the current path geometry reduces parasitic parameters only where critical, without affecting overall device functionality
2Loss of energy
If the loop area is minimized by positioning electrode pads in proximity, then parasitic parameters are reduced, but the manufacturing and connection precision requirements become more stringent
Solution Approach 1:
The patent determines an optimal minimum distance parameter between the first source electrode pad and second drain electrode pad that balances two competing requirements: reducing loop area to minimize parasitic parameters while maintaining sufficient tolerance for manufacturing and connection processes. This parameter optimization achieves the smallest practical loop area without making manufacturing impossible
3Speed
If a normally-on field-effect transistor is used, then low on-resistance and high-speed performance are achieved, but the device cannot block current at zero bias voltage
Solution Approach 1:
The patent segments the switching function into two separate field-effect transistors: a first normally-on FET that provides low on-resistance and high-speed performance, and a second normally-off FET that provides current blocking capability at zero bias. By dividing the functionality into separate components, the patent achieves both high-speed operation and safe current blocking without requiring a single transistor to simultaneously optimize both conflicting properties
Data Source
AI summary
According to a semiconductor device (101), a first switching active element (103) of a normally-on type and a second switching active element (104) of a normally-off type are cascode-connected to each other. This causes an electric current path to be formed. The first and second switching active elements (103, 104) are provided and connected so that loop area of the electric current path is a minimum area in a plan view of the semiconductor device (101).