Semiconductor Metal Plate Layout for Low-Inductance Series Packaging
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Solution Overview
Problem
Semiconductor devices with stacked electrodes face challenges in reducing inductance without increasing body size, particularly when an intermediate electrode is used, which can lead to larger device dimensions.
Innovation Solution
A semiconductor device configuration featuring a first and second semiconductor element connected in series, with metal plates arranged to face each other and insulate the semiconductor elements, allowing current paths to flow in opposite directions, thereby reducing inductance without the need for an intermediate electrode, thus maintaining a compact size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If an intermediate electrode is used to stack the positive electrode and negative electrode, then the inductance is reduced, but the body size increases
Solution Approach 1:
The patent removes the intermediate electrode from the stacked electrode configuration. By extracting this component, the patent eliminates the source of increased body size while maintaining the low-inductance benefit through alternative current path design in the planar layout.
Solution Approach 2:
The patent transitions from a three-dimensional stacked configuration to a two-dimensional planar arrangement. By changing the spatial dimension of electrode placement, the patent achieves low inductance through optimized current loop areas in the plane rather than through vertical stacking with intermediate electrodes.
2Object-affected harmful factors
If the positive electrode and negative electrode are stacked on top of another, then the inductance is reduced, but the device complexity increases
Solution Approach 1:
The patent divides the electrode system into separate positive and negative electrode regions arranged in a planar configuration. This segmentation allows independent optimization of each electrode area while maintaining simple current paths, avoiding the complexity of stacked multi-electrode assemblies.
Solution Approach 2:
The patent combines the functions of current conduction and electrode support into a single planar structure. By merging these functions into the substrate plane rather than requiring separate stacked components, the patent reduces device complexity while maintaining electrical performance.
Data Source
AI summary
In a semiconductor device, a first metal plate faces a first semiconductor element and a second semiconductor element and is electrically connected to a second terminal. A second metal plate faces the first metal plate while interposing the first semiconductor element between the first and second metal plates, and is electrically connected to a first terminal. A third metal plate faces the first metal plate while interposing the second semiconductor element between the first and third metal plates. The first semiconductor element has an electrode on a surface adjacent to the second metal plate and electrically connected to the second metal plate, and an electrode on a surface adjacent to the first metal plate and electrically connected to the third metal plate. The first semiconductor element is thermally connected to the first metal plate while being electrically insulated from the first metal plate by an insulator.