Semiconductor Devices with Low Junction Capacitance via Spaced Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in scaling down FETs while maintaining low junction capacitance, as SOI devices require extensive design changes and are costly, making direct migration from bulk CMOS to SOI technologies impractical due to floating body effects and high production costs.
Innovation Solution
The method involves forming semiconductor devices with isolation regions and recessing them to expose sidewalls, covering with spacers, and etching to create lateral openings, which are filled with a spin-on dielectric, allowing for reduced junction capacitance similar to SOI devices without floating body effects, while using bulk wafers to reduce production costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SOI devices are used to achieve low junction capacitance, then junction capacitance is reduced, but design complexity and production cost increase significantly
Solution Approach 1:
The substrate is divided into different regions: a first substrate region with a first conductivity type and a second substrate region with a second conductivity type. This segmentation allows the formation of n-type and p-type transistors in respective regions, enabling low junction capacitance through selective doping while maintaining compatibility with bulk CMOS processes.
Solution Approach 2:
Different regions of the substrate are assigned different conductivity types to create locally optimized transistor structures. The first substrate region is doped to form n-type transistors while the second substrate region is doped to form p-type transistors, allowing each region to have the optimal electrical characteristics for its intended transistor type.
2Reliability
If SOI technology is adopted to eliminate floating body effects, then transistor performance is improved, but production cost increases due to expensive starting substrates
Solution Approach 1:
The substrate conductivity type is changed in different regions through selective doping processes. By modifying the electrical parameters (conductivity type) of specific substrate regions, the invention achieves SOI-like performance characteristics without requiring expensive SOI starting substrates, thus reducing production costs while maintaining transistor performance.
3Ease of manufacture
If bulk devices are used to reduce production cost, then manufacturing cost is reduced, but junction capacitance increases compared to SOI devices
Solution Approach 1:
The bulk substrate is segmented into regions with different conductivity types, allowing the formation of transistors with reduced junction capacitance through selective doping. This approach maintains the cost advantage of bulk devices while achieving performance characteristics similar to SOI devices through localized electrical property modification.
Data Source
AI summary
Semiconductor devices with low junction capacitances and methods of fabrication thereof are described. In one embodiment, a method of forming a semiconductor device includes forming isolation regions in a substrate to form active areas. The sidewalls of the active areas are enclosed by the isolation regions. The isolation regions are recessed to expose first parts of the sidewalls of the active areas. The first parts of the sidewalls of the active areas are covered with spacers. The isolation regions are etched to expose second parts of the sidewalls of the active area, the second parts being disposed below the first parts. The active areas are etched through the exposed second parts of the sidewalls to form lateral openings. The lateral openings are filled with a spin on dielectric.