Semiconductor Lower Body Region Defect Engineering
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Solution Overview
Problem
The semiconductor device experiences a negative capacitance effect when turned on, leading to reduced gate-emitter capacitance and decreased reliability due to hole accumulation in the lower body region, causing variations in gate voltage and increased switching losses.
Innovation Solution
Incorporating a lower body region with a first range and a second range of higher crystal defect density, where the second range functions as recombination centers, reducing carrier lifetime and minimizing hole accumulation near the gate insulating film, thereby suppressing the negative capacitance effect.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If holes are accumulated in the lower body region to reduce drift region resistance, then power loss is reduced, but gate-emitter capacitance is reduced causing gate voltage variation and reliability decrease
Solution Approach 1:
The patent divides the lower body region into two distinct ranges with different crystal defect densities. The first range has lower crystal defect density to allow hole accumulation and reduce drift region resistance, while the second range has higher crystal defect density to serve as recombination centers that prevent excessive hole accumulation near the gate insulating film, thereby maintaining gate voltage stability and reliability.
2Power
If the intermediate region suppresses hole flow from collector to upper body region, then on-state performance is improved, but holes accumulate in the lower body region causing negative capacitance effect
Solution Approach 1:
The patent introduces a spatial differentiation within the lower body region by creating two ranges with different crystal defect densities. This local quality variation allows the first range to benefit from hole accumulation for improved on-state performance while the second range with higher defect density acts as a controlled recombination zone to prevent the negative capacitance effect.
Solution Approach 2:
The second range with higher crystal defect density acts as an intermediary zone between the hole accumulation region (first range) and the gate insulating film. This intermediary region provides controlled recombination centers that regulate hole distribution, preventing excessive hole accumulation near the gate insulating film while maintaining the beneficial hole accumulation in the drift region.
3Reliability
If crystal defect density is increased in the lower body region to reduce carrier lifetime, then hole accumulation is suppressed, but manufacturing complexity increases
Solution Approach 1:
Instead of uniformly increasing crystal defect density throughout the lower body region, the patent applies local quality variation by creating two distinct ranges. The second range with higher crystal defect density is specifically positioned to provide recombination centers, while the first range maintains lower defect density. This localized approach achieves the reliability improvement with minimal impact on manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively suppresses the negative capacitance effect, stabilizing the gate voltage and reducing current surges, enhancing the reliability and efficiency of the semiconductor device by preventing excessive hole accumulation and minimizing switching losses.
Implementation Method 1
the second range functions as recombination centers, reducing carrier lifetime and minimizing hole accumulation near the gate insulating film
Data Source
AI summary
The semiconductor substrate may include an emitter region, an upper body region being in direct contact with the gate insulating film below the emitter region, an intermediate region being in direct contact with the gate insulating film below the upper body region, a lower body region being in direct contact with the gate insulating film below the intermediate region, a drift region being in direct contact with the gate insulating film below the lower body region, and a collector region being in direct contact with the drift region from below. The lower body region may include a first range and a second range that has a higher crystal defect density than the first range. The second range may be in direct contact with the gate insulating film. The first range may be in direct contact with the second range on a side opposed to the gate insulating film.