Semiconductor Device Lower Select Gate Electrode Vertical Leveling
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Solution Overview
Problem
The challenge in semiconductor devices is to reduce defects in the channel hole-forming process, particularly due to misalignment and alignment errors during the formation of channel holes, which affects the manufacturing precision and storage capacity.
Innovation Solution
The semiconductor device design includes lower select gate electrodes arranged at different vertical levels, with specific insulating separation layers to prevent misalignment and ensure precise control during the manufacturing process, allowing for the formation of channel structures without a separate string separation insulating layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If lower select gate electrodes are arranged at the same vertical level, then the manufacturing process is simpler, but misalignment and alignment errors occur during channel hole formation
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement where all lower select gate electrodes are at the same level to a three-dimensional stacked arrangement where electrodes are positioned at different vertical levels. This dimensional change allows channel holes to be formed at different heights, eliminating misalignment issues while maintaining manufacturing feasibility through selective etching processes.
Solution Approach 2:
The patent divides the lower select gate electrodes into separate groups positioned at different vertical levels (first lower select gate electrodes at a first level, second lower select gate electrodes at a second level). This segmentation allows independent formation and alignment of channel holes at each level, preventing the propagation of alignment errors across the entire structure.
2Manufacturing precision
If a separate string separation insulating layer is added, then alignment precision is improved, but device complexity increases
Solution Approach 1:
The patent merges the string separation insulating layer with the existing lower select gate electrode structure. The insulating layer is positioned between the first and second lower select gate electrodes, serving both as a separator for different string groups and as part of the gate electrode assembly, thereby reducing overall device complexity while maintaining alignment precision.
3Manufacturing precision
If lower select gate electrodes are arranged at different vertical levels, then misalignment is reduced, but device complexity increases
Solution Approach 1:
By utilizing the vertical dimension to position lower select gate electrodes at different levels, the patent reduces misalignment in channel hole formation without requiring additional lateral separation structures. This vertical stacking approach maintains compact device geometry while improving manufacturing precision.
Solution Approach 2:
The insulating layer positioned between lower select gate electrodes at different levels serves multiple functions: it provides electrical isolation between gate electrodes, acts as a separator for different string groups, and facilitates the formation of channel holes at different vertical positions. This multi-functionality reduces the need for separate dedicated structures, thereby limiting the increase in device complexity.
Data Source
AI summary
Semiconductor devices are provided. The semiconductor devices may include a peripheral circuit structure, a memory cell block arranged on the peripheral circuit structure and including strings, each of which includes a lower select transistor, memory cell transistors, and an upper select transistor connected in series and stacked in a vertical direction, and bit lines on the memory cell block. The bit lines may include a first bit line electrically connected to first to third strings of the strings. The lower select transistors of the first to third strings include first to third lower select gate electrodes, respectively. The second lower select gate electrode may be arranged at a different vertical level from the first lower select gate electrode, and the third lower select gate electrode may be arranged at the same vertical level as the first lower select gate electrode.