Semiconductor Device With Lower Wiring Pattern For Vertical Channel Connection
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Solution Overview
Problem
Current semiconductor devices face challenges in achieving high integration and low manufacturing costs, particularly in connecting vertical channels to substrates without relying on selective epitaxial growth or opening floor surfaces of vertical holes, which can lead to process failures and affect electrical characteristics.
Innovation Solution
A semiconductor device design featuring a stack structure with vertically stacked gate electrodes, a channel structure including vertical and horizontal channels, and a lower wiring pattern with different widths, which electrically connects the channels to the substrate, omitting the need for selective epitaxial growth and potentially minimizing process failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If selective epitaxial growth is used to connect vertical channels to substrate, then electrical connection is achieved, but process failures occur and reliability deteriorates
Solution Approach 1:
The patent removes the selective epitaxial growth process from the manufacturing flow entirely. Instead, it uses a direct deposition method where the lower wiring pattern is formed by depositing conductive material (such as tungsten or copper) through a via structure that connects the vertical channel to the substrate, eliminating the need for selective epitaxial growth and its associated process failures.
Solution Approach 2:
The patent introduces a lower wiring pattern as an intermediary element between the vertical channel and the substrate. This wiring pattern serves as a mediator that provides reliable electrical connection without requiring selective epitaxial growth, thereby improving reliability while simplifying the manufacturing process.
2Reliability
If floor surfaces of vertical holes are opened for connection, then electrical connection is achieved, but gap-fill defects occur and reliability deteriorates
Solution Approach 1:
The patent performs preliminary actions by forming the lower wiring pattern in advance within a via structure before finalizing the vertical channel connection. The via is filled with conductive material through a controlled deposition process that ensures complete gap-fill without defects, eliminating the need to open floor surfaces later and preventing gap-fill defects.
Solution Approach 2:
The patent replaces the mechanical process of opening floor surfaces with a deposition-based approach. Instead of mechanically accessing the floor surface of vertical holes, the lower wiring pattern is deposited through a via that provides direct access to the connection point, eliminating mechanical intervention and associated gap-fill defects.
3Reliability
If conventional connection methods are used, then manufacturing process is simple, but un-etching defects occur and reliability deteriorates
Solution Approach 1:
The patent transitions from a two-dimensional planar connection approach to a three-dimensional vertical connection approach. The lower wiring pattern is formed in a via that extends vertically to connect the vertical channel to the substrate, utilizing the third dimension to achieve reliable connection without un-etching defects that plague conventional planar methods.
Data Source
AI summary
A stack structure including a plurality of gate electrodes is vertically stacked on a substrate and extends in a first direction. A channel structure includes vertical channels penetrating the stack structure and a horizontal channel connecting the vertical channels. The horizontal channel are provided under the stack structure. First lower wiring patterns are disposed between the substrate and the stack structure and electrically connected to the channel structure. Each first lower wiring pattern includes a first portion and a second portion having different widths from each other in the first direction.