Semiconductor LUN Selection Cycle to Reduce Command Overhead
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Solution Overview
Problem
Existing semiconductor systems face increased command overhead and complexity in NAND flash memory systems due to the use of separate command and address interfaces, which affects performance as operating frequencies increase.
Innovation Solution
A semiconductor system with a first and second semiconductor apparatus that utilizes a logical unit number (LUN) selection cycle to reduce command overhead by enabling command and address latch signals simultaneously, allowing for efficient data input and output operations through a unified bus system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a separate command address interface is used in NAND flash memory systems, then command overhead is reduced, but internal circuit complexity increases
Solution Approach 1:
The patent combines the command address interface and data interface into a unified bus structure, allowing command, address, and data signals to share the same physical transmission medium. This merging reduces the number of separate interfaces needed while maintaining efficient command execution through protocol-level separation of functions.
Solution Approach 2:
The unified bus structure is designed to perform multiple functions: transmitting commands, addresses, and data signals through the same physical interface. The interface can dynamically switch between different signal types based on the operational phase, making it a multi-functional component that reduces overall system complexity.
2Productivity
If operating frequency is increased in NAND flash memory systems, then productivity improves, but command overhead increases causing performance deterioration
Solution Approach 1:
The patent implements a pipeline architecture where command, address, and data phases are overlapped in time. While one operation is executing, the next command can be prepared and queued, allowing preliminary actions to be taken before the current operation completes. This reduces the impact of command overhead on overall throughput at high operating frequencies.
Solution Approach 2:
The unified bus structure enables continuous data transmission without idle cycles between command, address, and data phases. By eliminating bus switching overhead and maintaining continuous signal flow, the system sustains high productivity at increased operating frequencies without the performance deterioration caused by traditional command overhead.
Data Source
AI summary
A semiconductor system includes a first semiconductor apparatus and a second semiconductor apparatus. The first semiconductor apparatus transmits an address signal during an address cycle after transmitting a command signal during a command cycle. The first semiconductor apparatus transmits a selection signal during a logical unit number selection cycle before the command cycle. The second semiconductor apparatus performs a data input and output operation based on the selection signal, the command signal, and the address signal.