Semiconductor Device Staggered MAC Switching for Current Stability

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Solution Overview

Problem

In semiconductor devices performing neural network processing, sharp variations in current consumption occur due to the switching between active and idle periods, leading to fluctuations in power supply voltage, which complicates power supply design and increases costs.

Innovation Solution

The semiconductor device incorporates multiple multiplier accumulators, DMA controllers, and a dummy circuit to manage data transfer timing, allowing for the performance of dummy calculations and outputting dummy data, thereby reducing current consumption variations and stabilizing power supply voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If simultaneous switching of active and idle periods is carried out in multiple MAC circuits, then processing efficiency is improved and calculation throughput is increased, but sharp current consumption variations occur causing power supply voltage fluctuations

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidcurrent consumption variation
Core Design Contradiction:
ProductivityVSObject-generated harmful factors

Solution Approach 1:

The patent divides the n MAC circuits into multiple groups, where each group switches between active and idle periods at different times. This segmentation of the switching operations prevents simultaneous current consumption changes across all MAC circuits, thereby reducing sharp current variations and power supply voltage fluctuations while maintaining high processing efficiency through pipelined operation.

Inventive Principle:
Principle #1Segmentation

2Productivity

If simultaneous switching of active and idle periods is carried out in multiple MAC circuits, then processing efficiency is improved, but power supply design complexity increases due to voltage variation prevention requirements

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidpower supply design complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the MAC circuits into multiple groups with staggered switching schedules, which inherently reduces current consumption variations without requiring complex power supply design measures. This approach simplifies the power supply design by eliminating the need for expensive and complex voltage stabilization circuits while maintaining high processing efficiency.

Inventive Principle:
Principle #1Segmentation

3Productivity

If simultaneous switching of active and idle periods is carried out in multiple MAC circuits, then processing efficiency is improved, but design costs and manufacturing costs may be increased

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidmanufacturing cost
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The patent employs segmentation of MAC circuits into groups with different switching schedules, which reduces current consumption variations and power supply voltage fluctuations. This eliminates the need for expensive power supply stabilization components and complex design measures, thereby reducing both design costs and manufacturing costs while maintaining high processing efficiency.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS12182045B2Semiconductor device
Publication Date: 2024.12.31 RENESAS ELECTRONICS CORP
  • US12182045B2 patent drawing
  • US12182045B2 patent drawing
  • US12182045B2 patent drawing

AI summary

A semiconductor device capable of preventing a sharp variation in current consumption in neural network processing is provided. A dummy circuit outputs dummy data to at least one or more of n number of MAC circuits and causes the at least one or more of n number of MAC circuits to perform a dummy calculation and to output dummy output data. An output-side DMA controller transfers pieces of normal output data from the n number of MAC circuits to a memory, by use of n number of channels, respectively, and does not transfer the dummy output data to the memory. In this semiconductor device, the at least one or more of n number of MAC circuits perform the dummy calculation in a period from a timing at which the output-side DMA controller ends data transfer to the memory to a timing at which the input-side DMA controller starts data transfer from the memory.