Semiconductor Interconnection via Manganese Barrier Layer
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Solution Overview
Problem
In semiconductor device fabrication, existing methods face challenges in forming reliable metal interconnections with low resistance and precise via formation, particularly due to issues with metal oxide formation and alignment during the etching process, which affect the integrity and conductivity of the interconnection structures.
Innovation Solution
The method involves forming a seed layer with manganese on the substrate, converting it into a manganese oxide layer, and using a sequential stacking process of barrier layers, insulating layers, and metal layers, followed by etching and thermal treatment to create interconnection structures with barrier patterns and insulating patterns that allow for precise via formation without metal oxide formation on the metal interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a metal interconnection is formed using conventional methods, then the interconnection structure can be created, but metal oxide formation occurs on the metal interconnection surface degrading conductivity and reliability
Solution Approach 1:
A barrier layer is introduced as an intermediary between the metal interconnection and the environment. This barrier layer prevents direct exposure of the metal surface to oxidizing conditions during subsequent processing steps, thereby preventing metal oxide formation while maintaining the electrical conductivity of the copper interconnection.
Solution Approach 2:
The barrier layer is formed on the metal interconnection surface before any etching or processing steps are performed. This preliminary protective action ensures that the metal surface is already protected against oxidation before it is exposed to plasma or chemical environments in subsequent etching processes.
2Manufacturing precision
If etching is performed to form via holes, then via formation is achieved, but alignment precision deteriorates due to metal oxide interference
Solution Approach 1:
The barrier layer serves as an intermediary that allows etching processes to proceed without direct metal surface exposure. The etchant selectively removes the barrier layer to expose the metal interconnection at via locations while the barrier layer remains intact in other areas, enabling precise alignment without metal oxide interference.
Solution Approach 2:
The barrier layer is selectively removed at via locations through the etching process, creating local openings where metal interconnection exposure is needed. This local modification allows precise via formation while maintaining barrier protection in non-via areas, ensuring alignment precision.
3Reliability
If barrier layers and insulating layers are sequentially stacked, then interconnection structure integrity is improved, but fabrication process complexity increases
Solution Approach 1:
The barrier layer performs multiple functions: it prevents metal oxidation, serves as an etch stop layer during via formation, and provides a defined interface for subsequent insulating layer deposition. This multi-functionality reduces the need for additional separate process steps, managing fabrication complexity while maintaining structure integrity.
Solution Approach 2:
The interconnection structure uses a composite material system consisting of copper metal interconnection, silicon nitride barrier layer, and silicon oxide insulating layer. Each material is selected for its specific properties, and their combination creates a structure that maintains integrity while managing the fabrication process through well-defined material interactions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and conductivity of metal interconnections by preventing metal oxide formation and improving the alignment and filling of via holes, leading to improved semiconductor device performance and fabrication efficiency.
Implementation Method 1
performing an annealing process on the seed layer such that the manganese of the seed layer reacts with oxygen from the substrate to convert the seed layer into a manganese oxide layer or a manganese-silicon oxide layer
Implementation Method 2
performing an annealing process on the seed layer such that the manganese of the seed layer reacts with oxygen from the substrate
Data Source
AI summary
A method of fabricating a semiconductor device, the method including forming at least one interconnection structure that includes a metal interconnection and a first insulating pattern sequentially stacked on a substrate; forming barrier patterns covering sidewalls of the interconnection structure; forming second insulating patterns at sides of the interconnection structure, the second insulating patterns being spaced apart from the interconnection structure with the barrier patterns interposed therebetween; forming a via hole in the first insulating pattern by etching a portion of the first insulating pattern, the via hole exposing a top surface of the metal interconnection and sidewalls of the barrier patterns; and forming a via in the via hole.