Semiconductor Manufacturing Method for Narrower Pitch Line and Space Patterns
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Solution Overview
Problem
Current semiconductor manufacturing methods face challenges in forming fine patterns that are equal to or less than the resolution limit of lithography, as existing side wall transfer processes struggle to achieve narrower pitches and efficiently remove loop portions of spacer films.
Innovation Solution
A method involving the formation of first and second core films, spacer films, and subsequent etching processes to create line and space patterns with narrower pitches, utilizing spacer films as masks to achieve finer patterns and reduce process complexity by simultaneously removing loop portions during etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional side wall transfer process is used to form fine patterns, then the lithography resolution limit can be extended, but the process complexity increases due to the need to separately remove loop portions of spacer films
Solution Approach 1:
The patent merges the loop portion removal process with the main etching process by forming a second spacer film that serves as a mask during etching. This eliminates the need for a separate loop removal step, reducing process complexity while maintaining the ability to form fine patterns at narrower pitches
Solution Approach 2:
The patent segments the spacer film formation into multiple stages: first forming a spacer film to define the basic pattern, then forming a second spacer film specifically positioned to mask the loop portions during etching. This segmentation allows precise control over which portions are etched and which are protected
2Manufacturing precision
If the pitch of line patterns is reduced below the lithography resolution limit, then finer patterns are achieved, but the difficulty of forming accurate patterns increases
Solution Approach 1:
The patent uses spacer films as intermediary structures that translate the lithographically-formed core film pattern into the final fine line patterns. The spacer films are deposited conformally on the core films and then etched back, creating precise line patterns at narrower pitches without directly relying on lithography resolution
Solution Approach 2:
The spacer film formation process creates a copy of the core film pattern at a reduced pitch. The conformal deposition of spacer material on the core film sides automatically replicates the pattern geometry, enabling accurate pattern transfer at finer dimensions
3Manufacturing precision
If multiple separate processes are used to form patterns and remove loop portions, then pattern accuracy is maintained, but the manufacturing time increases
Solution Approach 1:
The patent combines multiple functions into a single etching process: the second spacer film serves simultaneously as the etch mask for creating line patterns and as the protective element that prevents loop portion formation. This merging of functions reduces the total number of process steps while maintaining pattern accuracy
Solution Approach 2:
The second spacer film is formed in advance before the etching process, pre-positioning the mask structures that will define both the line patterns and protect against loop portions. This preliminary action ensures that the subsequent etching process can proceed in a single step with both objectives achieved
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the creation of semiconductor devices with line and space patterns at narrower pitches than the lithography resolution limit, reducing process complexity and allowing for the formation of three-dimensionally intersecting patterns, suitable for advanced memory devices like resistance change type memory with a cross-point structure.
Implementation Method 1
processing the first film to be processed into a first line and space pattern which extends in the first direction and includes a pair of first line patterns connected at an end in the first direction via a loop portion, by an etching using the left first spacer film as a mask
Data Source
AI summary
According to one embodiment, a method for manufacturing a semiconductor device includes forming a plurality of second core films, the second core film having a first array portion, and a second array portion which is arranged so as to be spaced at a larger second space than the first space in the first direction from the first array portion, the second space being positioned above the loop portion. The method includes processing the second film to be processed below the first array portion into a second line and space pattern which includes a second line pattern extending in the second direction, and removing the second film to be processed below the second space and the loop portion of the first film to be processed, by an etching using the second spacer film as a mask.