Semiconductor Mark Design for Overlay Error Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scaling of semiconductor devices has led to overlay errors between circuit patterns and marks due to lens aberration during the lithography process, as marks need to be optically monitored and are larger than circuit patterns, causing improper alignment.
Innovation Solution
A semiconductor device manufacturing method that forms marks using patterns similar to device formation patterns, with specific resist patterns and etching processes to create recessed areas and pillar films, allowing for optical monitoring of mark positions and reducing overlay errors by using formulas to determine the size and arrangement of line patterns and hole patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If marks are made larger than circuit patterns for optical monitoring, then optical monitoring capability is improved, but overlay accuracy deteriorates due to lens aberration
Solution Approach 1:
The patent applies local quality by creating marks with different structural characteristics in different regions. Specifically, line patterns are formed with varying widths and spacing arrangements in different mark regions to optimize both optical detectability and overlay accuracy. The line-and-space patterns have different dimensional properties compared to the circuit patterns they overlay, allowing each region to be optimized for its specific function.
Solution Approach 2:
The patent utilizes parameter changes by systematically varying the dimensions of mark features. Line patterns are designed with specific width ratios (e.g., 2:1 or 3:1) and spacing arrangements that differ from circuit pattern dimensions. These parameter variations allow the marks to be sufficiently large for optical monitoring while incorporating design features that minimize sensitivity to lens aberration effects.
2Area of moving object
If circuit patterns are downsized for scaling, then device density is improved, but overlay error increases due to lens aberration affecting larger marks
Solution Approach 1:
The patent applies segmentation by dividing the mark structure into multiple discrete line patterns arranged in specific configurations. Instead of using single large mark features, the marks are segmented into multiple line-and-space patterns with controlled dimensions and spacing. This segmentation allows the overall mark to maintain large dimensional footprint for optical monitoring while individual line elements have dimensions that reduce aberration sensitivity.
Solution Approach 2:
The patent addresses the contradiction by transitioning from two-dimensional pattern scaling to three-dimensional structural design. While circuit patterns continue to scale down in the planar dimensions, the mark structures incorporate vertical dimension variations through etched recesses and filled regions. This dimensional transition allows marks to maintain optical detectability through enhanced contrast in the vertical dimension while keeping planar dimensions optimized for reduced aberration impact.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method improves pattern overlay accuracy and reduces overlay errors caused by lens aberration, enhancing the yield of semiconductor devices by allowing for precise optical monitoring of mark positions and alignment.
Implementation Method 1
a position of the processing target layer is recognized by using a mark, in a light exposure apparatus
Implementation Method 2
a first resist pattern that includes a first pattern including first components, and a mark including a second pattern provided with the first components and a third pattern not provided with the first components is formed
Implementation Method 3
a first recessed area is formed on the processing target layer, through the first resist pattern serving as a mask
Data Source
AI summary
According to an embodiment, a first resist pattern that includes a mark including a second pattern provided with first components and a third pattern not provided with the first components is formed. Then, a first recessed area is formed on a processing target layer using the first resist pattern. Thereafter, a second resist pattern that includes a fourth pattern is formed. The fourth pattern is formed such that the third pattern and part of the second pattern, which includes at least one row of the first components arranged along a periphery of the third pattern, are exposed. Then, a second recessed area is formed by using the second resist pattern. Thereafter, a position of the processing target layer is recognized by using a stepped portion formed at the second recessed area, in a light exposure apparatus, and a third resist pattern is formed.