Semiconductor Mark Structure for Overlay Precision
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Solution Overview
Problem
Existing semiconductor fabrication processes face challenges in achieving accurate overlay precision due to photoresist offset, rotation, shrinking, and resolution differences between overlay marks formed at different photoresist layers, affecting the detection of exposure errors and the formation of conductive structures.
Innovation Solution
A method and structure involving a substrate with a device region and a mark region, including first and second mark regions, where a dielectric layer and a conductive structure are formed with specific etching processes to create precise mark trenches and openings, allowing for accurate alignment and overlay precision measurement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If overlay marks are formed at the same position of different photoresist layers to measure exposure error, then overlay precision measurement is enabled, but resolution difference between marks affects detection accuracy
Solution Approach 1:
The patent applies local quality by creating different mark structures at different depths within the same dielectric layer. First marks are formed at a first depth while second marks are formed at a second depth, allowing each mark to be optimized for its specific detection requirements. This depth differentiation resolves the resolution consistency issue while maintaining measurement capability across multiple photoresist layers.
Solution Approach 2:
The patent transitions from two-dimensional mark positioning to three-dimensional mark positioning by utilizing vertical depth differentiation within the dielectric layer. Marks are positioned at different depths (first depth and second depth) rather than only at the same surface position, adding a vertical dimension to the mark structure that enables consistent resolution detection across multiple photoresist layers.
2Ease of manufacture
If photoresist layer is used for pattern transfer during exposure process, then wafer division into dies and scribe lanes is achieved, but photoresist offset and rotation affect overlay precision
Solution Approach 1:
The patent introduces a dielectric layer as an intermediary structure between the substrate and the photoresist layers. The mark structures are embedded within this dielectric layer rather than being formed directly in the photoresist, providing a stable reference framework that is independent of photoresist processing variations such as offset and rotation, thereby improving overlay precision measurement.
Solution Approach 2:
The patent performs preliminary action by pre-forming the mark structures within the dielectric layer before subsequent photoresist processing steps. These marks serve as predetermined reference features that remain stable throughout the photoresist coating, exposure, and development processes, enabling accurate overlay measurement despite photoresist variations.
3Reliability
If conductive structure is formed in openings through dielectric layer, then electrical connection is established, but alignment precision between openings and marks must be maintained
Solution Approach 1:
The patent implements feedback by using the embedded mark structures as reference features for measuring alignment precision during the fabrication process. The marks provide a measurable standard against which the positioning of openings and conductive structures can be verified, allowing for detection and correction of alignment deviations to maintain manufacturing precision.
Data Source
AI summary
The present disclosure provides mark structures and fabrication methods thereof. An exemplary fabrication process includes providing a substrate having a device region, a first mark region and a second mark region; sequentially forming a device layer, a dielectric layer and a mask layer on a surface of the substrate; forming a first opening in the dielectric layer in the device region, a first mark in the dielectric layer in the first mark region, and a mark opening in dielectric layer in the second mark region, bottoms of the first opening, the first mark and the mark opening being lower than a surface of the dielectric layer, and higher than a surface of the device layer; and forming a second opening in the dielectric layer on the bottom of the first opening and a second mark in the dielectric layer on the bottom of the mark opening.