Semiconductor Marker Layout Optimization via SPSO Algorithm
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Solution Overview
Problem
Conventional marker layout methods in photolithography processes for semiconductor manufacturing are inefficient due to random sampling and overfitting to experimental wafer data, leading to suboptimal overlay alignment and increased overlay errors in actual production stages.
Innovation Solution
A marker layout method using a sparse particle swarm optimization (SPSO) algorithm that determines the optimal number and location of markers by considering distance information and evaluating performance with fitness functions, ensuring robustness and uniformity to minimize overlay errors and irregularity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If more markers are allocated on a wafer to improve overlay error correction accuracy, then overlay alignment precision is improved, but turn around time is extended and process efficiency deteriorates
Solution Approach 1:
The patent changes the parameter of marker quantity from 'more is better' to 'optimal number sufficient for accuracy'. By determining that a limited number of markers (e.g., 3-5 per field) is sufficient when optimally positioned, the patent resolves the contradiction between using more markers for accuracy and maintaining process efficiency.
Solution Approach 2:
The patent applies local quality by strategically positioning markers in specific locations within each field rather than uniformly distributing them. The marker layout is optimized locally in each field based on overlay error characteristics, ensuring maximum measurement effectiveness with minimum marker count.
2Ease of manufacture
If conventional rule-based approaches with random sampling are used to determine marker layout, then implementation is simple, but reliable performance cannot be ensured due to randomness and overfitting
Solution Approach 1:
The patent introduces feedback by using measured overlay errors from pilot wafers to iteratively optimize the marker layout for production wafers. The system continuously refines marker positions based on actual measurement data, eliminating random sampling and ensuring reliable, consistent performance across all wafers.
Solution Approach 2:
The patent performs preliminary action by determining the optimal marker layout in advance using pilot wafer data before actual production. This pre-optimization ensures that the marker layout is tailored to the specific tool and process conditions, guaranteeing reliable performance from the start of production.
3Stability of the object's composition
If markers are evenly distributed on the overall wafer using specific rules, then spatial distribution uniformity is improved, but overlay alignment effect is not maximized
Solution Approach 1:
The patent applies local quality by optimizing marker positions independently in each field rather than uniform distribution across the entire wafer. This allows marker density and positioning to be adapted to local overlay error characteristics in different fields, maximizing measurement precision while maintaining sufficient spatial coverage.
Solution Approach 2:
The patent changes the parameter of marker distribution from 'uniform across wafer' to 'optimized per field'. By allowing different marker configurations in different fields based on local conditions, the system achieves both spatial coverage and maximum overlay correction effectiveness.
Data Source
AI summary
A method of determining a marker layout for a semiconductor device includes determining the number of markers to be used in a field of a wafer using a first fitness function, calculating a marker probability distribution considering distance information among the markers and determining locations of a marker to be used according to the marker probability distribution, and evaluating performance of a final marker layout by using a second fitness function. The method provides an optimized approach to marker layout, so that the quality of a marker layout may be enhanced. Also, the method generates a marker layout that may minimize a prediction value of an overlay error of experimental wafers and an irregularity of marker locations, so that robust performance may be ensured for the prediction of overlay errors for subsequent new wafers.