Semiconductor Package Marking With Discontinuous Dot Grid

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Solution Overview

Problem

Conventional engraving markings on semiconductor packages face visibility issues due to the decreasing thickness of the mold layer, leading to low visibility and potential reliability problems when dot markings are in contact or overlap.

Innovation Solution

The use of embossed dot markings arranged discontinuously in vertical and horizontal directions on a semiconductor package, with an effective area less than half the total area of the display region, to maintain visibility and reduce thickness variation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional engraving markings are used on the mold layer, then markings can be formed to display information, but visibility decreases and reliability problems occur when the mold layer thickness decreases

Engineering Contradiction:

Improvemarking reliabilityVSAvoidmold layer thickness

Core Design Contradiction:

ReliabilityVSLength of stationary object

Solution Approach 1:

The marking is segmented into discrete dot markings arranged in a grid pattern rather than continuous engraving. This segmentation allows the markings to maintain visibility and structural integrity even when the mold layer thickness is reduced, as the discrete dots require less material depth to maintain contrast and readability.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The dot markings are designed with specific local characteristics including controlled effective area (less than 50% of unit display region), specific spacing, and discontinuous arrangement. These local quality parameters ensure that each dot maintains sufficient visibility while the overall marking structure remains reliable on thin mold layers.

Inventive Principle:

Principle #3Local quality

2Illumination intensity

If dot markings are arranged densely to improve visibility, then marking visibility increases, but thickness variation increases and reliability decreases due to contact or overlap

Engineering Contradiction:

Improvemarking visibilityVSAvoidmarking reliability

Core Design Contradiction:

Illumination intensityVSReliability

Solution Approach 1:

The dot markings are arranged with effective area occupying less than 50% of each unit display region, providing partial coverage that maintains visibility while preventing excessive density. This partial action approach ensures dots remain visually distinct without contacting or overlapping adjacent dots, maintaining structural reliability.

Inventive Principle:

Principle #16Partial or excessive action

Solution Approach 2:

The dot markings are arranged in a discontinuous pattern with asymmetric spacing in vertical and horizontal directions, preventing uniform contact or overlap while maintaining visual distribution. This asymmetric arrangement ensures that no two dots touch while preserving visibility across the marking area.

Inventive Principle:

Principle #4Asymmetry

3Illumination intensity

If the effective area of dot markings is increased to improve visibility, then marking visibility improves, but thickness variation increases leading to reliability issues

Engineering Contradiction:

Improvemarking visibilityVSAvoidthickness variation

Core Design Contradiction:

Illumination intensityVSLength of stationary object

Solution Approach 1:

The effective area of dot markings is precisely controlled as a critical parameter, set to less than 50% of the unit display region area. This parameter optimization balances visibility requirements with thickness variation constraints, ensuring that dots are large enough to be visible but small enough to prevent excessive material displacement and thickness variation.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS9035308B2Semiconductor package and method of fabricating the same

Publication Date: 2015.05.19 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor package, comprising: a semiconductor substrate; a mold layer on the semiconductor substrate; and a marking formed on a surface of the mold layer, the marking comprising dot markings substantially discontinuously arranged in vertical and horizontal directions of a display region. An effective area of the dot markings within a unit display region of the marking is smaller than about half a total area of the unit display region.