Semiconductor Layout Adaptation via Marking Layers
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Solution Overview
Problem
The existing semiconductor integrated circuit (IC) design process is time-consuming and costly when changes in semiconductor device characteristics require the creation of new layouts, particularly for fin field-effect transistors (fin FETs), as it involves redesigning the entire layout rather than adapting existing ones.
Innovation Solution
A method that involves creating a marking layer indicating changes in width, height, or space of semiconductor devices, such as fin FETs, based on changes in characteristics, and applying this marking layer to a previously created layout to generate a new library without altering the layout, ensuring constant pitch and satisfying design rules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a new layout is created to accommodate changes in semiconductor device characteristics, then the design can satisfy new electrical and thermal requirements, but the design time and cost increase significantly
Solution Approach 1:
The patent applies preliminary action by pre-defining multiple marking layers that represent different device characteristic variations (width, height, space) before the actual design change is needed. When electrical or thermal characteristics require adjustment, the corresponding pre-prepared marking layer is simply applied to the existing layout, avoiding the need to create new layouts from scratch and significantly reducing design time while meeting new requirements
Solution Approach 2:
The patent employs parameter changes by using marking layers that encode specific dimensional modifications (width, height, space parameters) of semiconductor devices. By applying different marking layers, the layout adapts to various electrical and thermal characteristic requirements through parameter adjustment rather than complete redesign, thus maintaining reliability while minimizing design time loss
2Adaptability or versatility
If the layout is redesigned to reflect changes in semiconductor device characteristics, then the new design can accommodate different device dimensions, but the complexity of the design process increases
Solution Approach 1:
The patent applies segmentation by dividing the layout modification process into distinct, independent marking layers, each representing a specific type of device characteristic change (width, height, or space). This segmentation allows designers to selectively apply only the necessary marking layers for the required adaptation, avoiding the complexity of redesigning the entire layout and simplifying the overall design process while maintaining high adaptability
Solution Approach 2:
The patent implements universality by creating a set of marking layers that can be applied to various semiconductor devices throughout the layout to achieve different dimensional adaptations. These marking layers serve multiple functions: they can be applied individually or in combination, work with different device types, and accommodate various characteristic changes, thereby providing a universal solution that reduces design process complexity while enhancing adaptability
3Adaptability or versatility
If a new library is created with modified device characteristics, then the library can support updated device specifications, but the creation time and resource consumption increase
Solution Approach 1:
The patent applies copying by creating marking layers that replicate the effect of device characteristic changes without actually modifying the original layout or creating a completely new library. The marking layers copy the dimensional adjustments needed for updated device specifications and can be overlaid on existing layouts, enabling rapid adaptation to new specifications while maintaining high library creation productivity
Solution Approach 2:
The patent uses preliminary action by pre-defining marking layers that encapsulate various device characteristic modifications before they are needed. When updated device specifications are required, the appropriate pre-prepared marking layers are applied to the existing library, allowing rapid adaptation to new specifications without time-consuming library recreation and maintaining high productivity
Data Source
AI summary
According to example embodiments of inventive concepts, a method of designing a semiconductor integrated circuit includes: creating a marking layer that indicates at least one semiconductor device of a plurality of semiconductor devices that is to be changed in at least one of width, height, and space thereof from an adjacent semiconductor device; and applying the marking layer to a previously created layout to generate a new library of the at least one semiconductor device that is changed in at least one of width, height, and space from an adjacent semiconductor device. The marking layer may be based on a change in characteristics of the at least one semiconductor device of the plurality of semiconductor devices.