Semiconductor Design System Mask Alignment Verification
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Solution Overview
Problem
The increasing density of features on substrates due to decreasing technology nodes often exceeds the resolution capabilities of single mask lithography processes, leading to mismatches when multiple masks are used, which can cause circuit failures and reduce production yield, and existing manual verification methods are prone to errors.
Innovation Solution
A semiconductor device designing system that includes a schematic design block, netlist file, pre-coloring information extraction block, layout design block, layout versus schematic comparison block, and layout parasitic extraction block, which use pre-coloring information to accurately assign features to masks and compare designs, reducing mismatches and improving verification accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple masks are used to transfer layout design to wafer, then the density of features can be increased beyond single mask resolution capability, but mask related mismatches occur causing circuit failures and reduced production yield
Solution Approach 1:
The system performs preliminary verification by automatically comparing the layout design against the schematic design before mask production. This preliminary check identifies potential mismatches and errors in feature assignment to masks, allowing corrections to be made before manufacturing begins, thus preventing circuit failures and improving production yield.
Solution Approach 2:
The system provides feedback by automatically verifying the layout design against the schematic design and reporting any mismatches or errors. This feedback mechanism allows designers to review and correct potential issues in mask assignment, ensuring that features are correctly assigned to masks and reducing the likelihood of circuit failures.
2Ease of manufacture
If manual verification is used to confirm layout design accuracy, then the process is simple to implement, but errors are overlooked reducing verification reliability
Solution Approach 1:
The system replaces manual verification with an automated computer-based verification process. The automated system compares the layout design against the schematic design using computational algorithms, eliminating human error and providing reliable verification of feature assignment to masks, while maintaining ease of implementation through automated scripts and tools.
3Adaptability or versatility
If features are assigned to masks based on manual layout design, then the design process is flexible, but mismatches occur due to human error
Solution Approach 1:
The system provides automated feedback by comparing the layout design against the schematic design and identifying mismatches in feature assignment to masks. This feedback mechanism maintains design flexibility while improving manufacturing precision by automatically detecting and reporting alignment errors, allowing designers to correct mismatches before mask production.
Solution Approach 2:
The system replaces manual verification with automated computational comparison between layout and schematic designs. This automated approach maintains the flexibility of manual design processes while significantly improving manufacturing precision by eliminating human error in feature assignment and alignment verification.
Data Source
AI summary
A circuit design system includes a schematic design tool configured to generate schematic information and pre-coloring information for a circuit. The circuit design system also includes a netlist file configured to store the schematic information and the pre-coloring information on a non-transitory computer readable medium and an extraction tool configured to extract the pre-coloring information from the netlist file. A layout design tool, included in the circuit design system, is configured to design at least one mask based on the schematic information and the pre-coloring information. The circuit design system further includes a layout versus schematic comparison tool configured to compare the at least one mask to the schematic information and the pre-coloring information.