Semiconductor Light Emitting Device Mask Alignment
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Solution Overview
Problem
The manufacturing process of semiconductor light emitting devices often results in defects due to inaccurate alignment and vacancies during the packaging process, leading to reduced production yield and efficiency.
Innovation Solution
A method involving a mask with openings on a base, where semiconductor light emitting chips are precisely placed and aligned using a device carrier that recognizes the mask's pattern, and an encapsulant is supplied through the openings to cover the chips, with the mask serving as a dam to ensure accurate positioning and alignment, reducing defects and increasing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional packaging process is used without mask alignment, then process speed is maintained, but alignment precision and manufacturing yield deteriorate due to inaccurate chip positioning and vacancies
Solution Approach 1:
The mask is prepared in advance with precise opening patterns that define the exact positions where semiconductor light emitting chips should be placed. This preliminary structuring of the base with pre-defined alignment features enables accurate chip positioning during the packaging process without requiring complex real-time alignment adjustments, thus maintaining high production efficiency while achieving precise alignment.
Solution Approach 2:
The mask serves as an intermediary component between the base and the semiconductor light emitting chips. It provides a physical template with openings that guides the placement of chips, ensuring they are positioned accurately at the intended locations. This intermediary structure eliminates the need for complex alignment mechanisms while maintaining precise positioning, resolving the contradiction between alignment precision and production efficiency.
2Manufacturing precision
If additional correction and filling processes are implemented to address alignment defects, then manufacturing precision improves, but process complexity and production time increase
Solution Approach 1:
The mask is designed with pre-defined opening patterns that correspond exactly to the desired chip placement locations. By preparing this alignment template in advance, the system ensures that chips are placed accurately from the beginning, eliminating the need for subsequent correction and filling processes. This preliminary structuring simplifies the overall manufacturing process while maintaining high precision.
Solution Approach 2:
The base is segmented into multiple discrete opening regions through the mask structure, with each opening corresponding to a specific chip placement location. This segmentation approach allows for independent, precise placement of each chip at its designated position, ensuring accurate alignment without requiring complex post-processing corrections for misaligned chips.
3Productivity
If high-speed sorting and placement is performed without precision control, then productivity increases, but alignment accuracy and defect rate worsen
Solution Approach 1:
The mask acts as a physical intermediary that guides high-speed chip placement without requiring complex real-time alignment control systems. The pre-formed opening patterns in the mask provide automatic positional reference, allowing chips to be placed at high speed while maintaining accurate alignment through the mask's structural guidance rather than through complex active control mechanisms.
Solution Approach 2:
The mask structure provides self-aligning features through its pre-defined opening patterns. When the base with mask is positioned in the packaging equipment, the mask's geometric features automatically establish the correct coordinate system for chip placement. This self-service alignment mechanism enables high-speed operation without sacrificing precision, as the system does not require complex sensing and adjustment during the high-speed placement process.
Data Source
AI summary
Disclosed is a method for manufacturing a semiconductor light emitting device, the method including: providing a mask having a plurality of openings on a base; placing semiconductor light emitting chips on exposed portions of the base through the openings, respectively, by a device carrier which recognizes a shape of the mask and calibrates position for a semiconductor light emitting chip to be seated; and supplying an encapsulant to each of the openings, with the mask serving as a dam.