Semiconductor Mask Stack Grid Patterning via Double Etching
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Solution Overview
Problem
Current double patterning techniques in semiconductor fabrication face challenges in achieving high aspect ratio features and reduced pitch separation due to resolution limitations of photolithography equipment, affecting the horizontal integration density of semiconductor devices like DRAM.
Innovation Solution
The method involves forming a mask stack with multiple layers and using anisotropic etching to create grid-type patterns over the device layer, allowing for the formation of contact holes with reduced pitch separation and improved uniformity, enabling higher aspect ratio features and enhanced integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography technique is used for patterning, then manufacturing process is simple, but manufacturing precision deteriorates due to resolution limitations
Solution Approach 1:
The patent applies segmentation by dividing the single patterning step into multiple sequential patterning operations. First, a preliminary pattern is formed using photolithography, then spacer material is deposited and etched to create additional patterns at reduced pitch separation. This multi-stage approach overcomes the resolution limitations of conventional photolithography while managing process complexity through systematic breakdown of the patterning task.
Solution Approach 2:
The patent employs preliminary action by first forming a preliminary pattern that serves as a template for subsequent patterning steps. This preliminary pattern is created using conventional photolithography, then used as a foundation for depositing spacer material and performing selective etching to achieve the final reduced-pitch pattern. The preliminary action enables the system to work around equipment resolution limits.
2Productivity
If conventional patterning technique is used, then device integration density is limited, but manufacturing process remains simple
Solution Approach 1:
The patent applies dimensionality change by transitioning from two-dimensional planar patterning to three-dimensional spacer-based patterning. By depositing conformal spacer layers around preliminary pattern structures and then performing anisotropic etching, the process creates features with reduced pitch separation in the horizontal plane. This dimensional transition enables higher integration density while the systematic multi-layer approach manages fabrication complexity.
Solution Approach 2:
The patent employs the nested doll principle by creating patterns within patterns through multiple patterning cycles. The preliminary pattern structures serve as templates that are subsequently surrounded by spacer material, which itself becomes a template for further pattern formation. This nested approach allows progressive reduction of pitch separation and increase in horizontal integration density through iterative application of the patterning sequence.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the fabrication of semiconductor devices by improving the formation of high aspect ratio features and reducing pitch separation, thereby increasing horizontal integration density and overcoming the limitations of existing photolithography techniques.
Implementation Method 1
performing anisotropic etching to create grid-type patterns over the device layer
Data Source
AI summary
A method is disclosed, which comprises forming a mid layer over a mask stack that is over a device layer of a substrate; forming a first buffer layer on the mid layer and a plurality pairs of first linear patterns over the first buffer layer; deposing a spin on hard mask layer filling between the first linear patterns; forming a second buffer layer on the spin on hard mask layer and a plurality of second linear patterns on the second buffer layer that projectively intercepts the first linear patterns; performing a mid layer opening process by concurrently etching the second buffer layer, the spin on hard mask layer, and the first buffer layer through the first and the second linear patterns to partially expose the mid layer; and etching the exposed portions of the mid layer to form a grid-type pattern over the mask stack.