Semiconductor Mask Structure for BEOL Overlay Accuracy
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Solution Overview
Problem
Existing double patterning technologies in semiconductor manufacturing face challenges with low overlay accuracy and limited process windows, particularly in the Back End Of Line (BEOL) process, which complicates the formation of semiconductor structures with smaller critical dimensions.
Innovation Solution
A semiconductor structure forming method that involves a multi-layered mask structure with specific opening configurations and side wall layers, where the second mask layer has multiple openings exposing the first mask layer, and side wall layers are formed to enhance the process window and overlay accuracy by using these layers as masks for etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If double patterning technology is used to form smaller critical dimensions, then the lithography limit is improved, but the overlay accuracy deteriorates
Solution Approach 1:
The patent segments the patterning process into multiple distinct steps with separate mask layers (first mask layer, second mask layer, third mask layer) and intermediate etching steps. This segmentation allows each layer to be optimized independently, with the first mask layer forming initial patterns, the second mask layer creating intermediate structures with side wall layers, and the third mask layer completing the final pattern, thereby achieving both small critical dimensions and high overlay accuracy
Solution Approach 2:
The patent introduces intermediate structures including side wall layers formed between the first and second mask layers, and intermediate etching steps that create transition patterns. These intermediary elements act as mediators that transfer and refine patterns between mask layers, improving overlay accuracy by providing stable reference structures and reducing direct dependency between subsequent lithography steps
2Manufacturing precision
If photoresist is used twice in LELE and LLE technologies, then the lithography limit is improved, but the manufacturing cost increases
Solution Approach 1:
The patent changes the material parameter by replacing photoresist with metal mask layers in the second and third patterning steps. This parameter change eliminates the need for repeated photoresist application and baking processes, reducing manufacturing cost while maintaining the ability to achieve small critical dimensions through precise metal layer patterning and etching
3Ease of manufacture
If the process window is enlarged by adding side wall layers, then the process difficulty is reduced, but the device complexity increases
Solution Approach 1:
The patent applies preliminary action by forming side wall layers in advance before the third mask layer patterning step. These pre-formed side wall structures serve as protective barriers and alignment references that simplify subsequent etching processes, enlarging the process window and reducing process difficulty despite the additional structural complexity introduced
Data Source
AI summary
The present disclosure provides a semiconductor structure forming method, including: providing a base, a first mask layer and a second mask layer located at the top of the first mask layer being formed on the base, and the second mask layer internally having a first opening, a second opening and a third opening; forming first side wall layers on a side wall of the first opening, a side wall of the second opening and a side wall of the third opening; forming a first pattern layer filling the first opening, the second opening and the third opening, the first pattern layer internally having a first groove; etching to remove the second mask layer located between the second opening and the third opening along the bottom of the first groove, so as to form fourth openings located between adjacent first side wall layers; and by using the second mask layer and the first side wall layers as masks, etching the first mask layer below the first opening, the second opening, the third opening and the fourth openings, so as to form a patterned first mask layer. The present disclosure can enlarge a process window and improve the position accuracy of the formed patterned first mask layer.