Semiconductor Mask Pattern for Sub-30 nm Hole Patterning
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Solution Overview
Problem
In semiconductor device fabrication, particularly in DRAM processes, hole patterning with parameters below 30 nm is challenging due to insufficient overlay margins, leading to poor patterning and formation of poorly shaped holes when using spacer patterning technologies, especially when a periphery-close mask is not sufficient or necessary.
Innovation Solution
A method involving a combination of negative spacer pattern technology (NSPT) and positive spacer patterning technology (PSPT) processes to form a mask pattern with a mesh type structure and blocking patterns, which prevents poor patterning in the cell matrix edge region without requiring a periphery-close mask, allowing for precise hole formation in the semiconductor device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If a periphery-close mask (PCM) is used to cover the peripheral region in positive SPT process, then etching of the peripheral region is prevented, but overlay between the PCM and the cell matrix region is insufficient leading to poor patterning
Solution Approach 1:
The mask pattern is divided into multiple regions: a first region corresponding to the cell matrix region with line patterns for hole formation, and a second region corresponding to the peripheral region with blocking patterns. This segmentation allows different functional requirements to be met in different regions without compromising overlay precision.
Solution Approach 2:
The mask pattern applies different structures to different regions: line patterns in the first region for precise hole patterning and blocking patterns in the second region for peripheral protection. This local differentiation enables each region to have the specific quality needed for its function while maintaining overall overlay precision.
2Manufacturing precision
If negative SPT process is performed twice without PCM, then overlay margin is improved, but the structure of etch mask in peripheral region becomes complicated
Solution Approach 1:
The mask pattern serves multiple functions simultaneously: it defines holes in the cell matrix region through line patterns and protects the peripheral region through blocking patterns. This multi-functionality eliminates the need for separate PCM and simplifies the overall process while maintaining good overlay margins.
3Reliability
If positive SPT process is performed without sufficient overlay, then holes may be defined partially or in undesired manner, but using PCM to ensure coverage worsens the overlay precision
Solution Approach 1:
The mask pattern extends into the peripheral region in the planar dimension, providing lateral coverage for hole definition. This dimensional extension ensures that holes are properly defined at the boundaries of the cell matrix region without requiring vertical stacking of multiple masks, thereby maintaining overlay precision.
Data Source
AI summary
A method for fabricating a semiconductor device includes forming an etching target layer over a substrate including a first region and a second region; forming a hard mask layer over the etching target layer; forming a first etch mask over the hard mask layer, wherein the first etch mask includes a plurality of line patterns and a sacrificial spacer layer formed over the line patterns; forming a second etch mask over the first etch mask, wherein the second etch mask includes a mesh type pattern and a blocking pattern covering the second region; removing the sacrificial spacer layer; forming hard mask layer patterns having a plurality of holes by etching the hard mask layer using the second etch mask and the first etch mask; and forming a plurality of hole patterns in the first region by etching the etching target layer using the hard mask layer patterns.