Semiconductor Mask Layer Structure for Precise Pattern Replication
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Solution Overview
Problem
The challenge of achieving higher integration in semiconductor devices is intensified by the need for new exposure technologies and high-cost techniques due to the miniaturization of patterns, making it difficult to replicate identical shapes accurately in nanometer scales.
Innovation Solution
A semiconductor device structure is designed with a substrate, gate insulating film, gate electrode, capping film, gate spacer, insulating liner, insulating layer, mask layer, and plug, along with a method of manufacturing that includes forming a main hole, mask layer, and plug hole to enhance integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If new exposure technologies and high-cost techniques are used, then pattern replication accuracy is improved, but manufacturing cost increases
Solution Approach 1:
The mask layer is divided into multiple functional regions: a first region with a first line width and a second region with a second line width. This segmentation allows different portions of the circuit pattern to be formed with different precision requirements, enabling cost-effective manufacturing while maintaining overall pattern accuracy.
Solution Approach 2:
Different line widths are assigned to different regions of the mask layer based on local requirements. The first line width is used in regions requiring higher precision, while the second line width is used in regions where standard precision suffices, optimizing the balance between manufacturing cost and pattern replication accuracy.
2Productivity
If pattern line widths are reduced for higher integration, then device integration is improved, but exposure technology requirements and manufacturing cost increase
Solution Approach 1:
The mask layer is segmented into multiple regions with different line widths. By dividing the pattern into regions that can be manufactured with existing exposure technologies, the patent enables higher device integration without requiring advanced exposure tools for the entire structure.
Solution Approach 2:
The patent introduces variability in the vertical dimension by creating mask layers at different heights or thicknesses, corresponding to different line width regions. This dimensional approach allows complex high-integration patterns to be formed using standard exposure technologies applied to simplified two-dimensional mask regions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables precise replication of tiny patterns without errors, facilitating higher integration and reducing manufacturing costs by utilizing a structured semiconductor device design.
Implementation Method 1
The photoresist coating on the wafer undergoes a chemical reaction only in the areas exposed to light, resulting in a difference in solubility between the exposed and unexposed areas
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes: a substrate; a first gate insulating film on the substrate; a first gate electrode on the first gate insulating film; a first capping film on the first gate electrode; a first gate spacer in contact with the first gate insulating film, the first gate electrode, and the first capping film; an insulating liner on the first capping film and the first gate spacer; an insulating layer on at least a portion of the first gate spacer and defining a main hole; a mask layer including a base part on an upper surface of the insulating layer, and a pillar part extending into the main hole and contacting the substrate; and a plug provided in the main hole and surrounded by the pillar part of the mask layer.