Semiconductor Mask Layer Patterning Beyond Lithography Limits
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Solution Overview
Problem
As DRAM technology advances towards smaller dimensions, the feature size of exposure lines approaches the theoretical resolution limit, leading to severe distortion of imaging on silicon wafers and degradation of photolithography image quality, hindering further reduction in minimum line width and spacing of integrated circuit design.
Innovation Solution
A method of manufacturing semiconductor devices involves forming patterned first and second mask layers on a layer to be etched, where these layers jointly define an opening to expose the layer for etching, allowing for larger feature sizes of the masks while maintaining the same device feature size, enabling further reduction in device size, improving yield, and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the feature size of exposure lines is reduced to achieve smaller device dimensions, then device miniaturization is improved, but photolithography image quality deteriorates due to severe distortion approaching the theoretical resolution limit
Solution Approach 1:
The patent divides the single mask layer into two separate mask layers (first mask layer and second mask layer). Each mask layer can be formed with larger, less distorted features using conventional photolithography, avoiding the image quality degradation that occurs when attempting to directly pattern sub-resolution features in a single step.
Solution Approach 2:
The patent transitions from a two-dimensional single-layer mask approach to a three-dimensional multi-layer mask structure. By stacking multiple mask layers at different heights and using selective etching, the patent achieves fine device features while maintaining larger, higher-quality mask patterns in each individual layer.
2Productivity
If the minimum line width and spacing are reduced to increase circuit capacity per chip, then functionality and capacity are improved, but manufacturing difficulty increases due to photolithography limitations
Solution Approach 1:
The patent segments the patterning process into multiple steps with separate mask layers, allowing each mask to be manufactured with relaxed dimensional constraints. This maintains ease of manufacture while achieving the fine line widths and spacing needed for higher circuit capacity through the combined pattern of multiple masks.
Solution Approach 2:
The patent performs preliminary patterning actions by forming multiple mask layers with larger, easier-to-manufacture features before the final etching step. This preliminary structuring enables subsequent processes to achieve fine features without directly confronting the photolithography resolution limits during the critical patterning step.
3Ease of manufacture
If larger mask feature sizes are used to improve manufacturing ease, then ease of manufacture is improved, but device feature size reduction is limited
Solution Approach 1:
The patent uses the vertical dimension by stacking multiple mask layers at different heights. Each mask layer can use larger feature sizes for ease of manufacture, but the combination of these layers through selective etching creates smaller effective device features, thus resolving the contradiction between mask size and device size.
Solution Approach 2:
The patent implements a nested structure where multiple mask layers are positioned relative to each other, with each layer contributing to the final pattern. The larger features of individual masks nest together to define the smaller final device features, allowing ease of manufacture at the mask level while achieving miniaturization at the device level.
Data Source
AI summary
Embodiments provide a semiconductor device and a method of manufacturing the same. The method includes: providing a layer to be etched; forming a patterned first mask layer on the layer to be etched; and forming a patterned second mask layer formed on the layer to be etched, where the second mask layer and the first mask layer jointly define an opening, which exposes the layer to be etched; and etching the layer to be etched using the first mask layer and the second mask layer as masks, thus forming a pattern to be etched. The above-described method of manufacturing the semiconductor device allows the feature size of the first mask layer and the second mask layer to be relatively larger while keeping the device feature size the same, makes it possible to further reduce the feature size of the device.