Semiconductor Mask Patterning With Quadruple Spacers for Reliable Line Widths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor manufacturing methods face challenges in achieving precise and reliable patterning of semiconductor devices, particularly in the peripheral circuit regions, leading to potential defects and reduced electrical reliability.
Innovation Solution
A method involving a quadruple patterning technique (QPT) is employed, which includes forming a mask layer structure with multiple layers, using photoresist patterns to etch these layers sequentially, and forming spacers and mandrel patterns to create precise active patterns, thereby enhancing the patterning process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional single-step patterning is used, then manufacturing process is simple, but patterning precision and electrical reliability deteriorate
Solution Approach 1:
The patterning process is divided into multiple sequential steps (first patterning step forming mandrel patterns, second patterning step forming final patterns) with intermediate spacer formation. This segmentation allows each step to achieve optimal precision without overwhelming complexity in a single step, resolving the contradiction between precision and process simplicity.
Solution Approach 2:
The invention introduces vertical dimension through multi-layer mask structures (first mask layer, second mask layer, buffer layer) and spacer formation on sidewalls. This dimensional expansion enables precise pattern transfer that cannot be achieved with conventional planar single-step patterning, improving precision while managing complexity through structured layering.
2Length of moving object
If feature size is reduced for down-scaling, then device density increases, but electrical reliability and pattern precision deteriorate
Solution Approach 1:
Mandrel patterns are formed first as preliminary structures before the final pattern formation. These mandrels serve as precursors that guide subsequent spacer formation and pattern transfer, enabling precise control of final feature dimensions even at reduced feature sizes through the intermediate guiding structure.
Solution Approach 2:
Spacers act as intermediary structures formed on the sidewalls of mandrel patterns. These spacers mediate the transformation from mandrel dimensions to final pattern dimensions, providing an additional control mechanism for feature size and precision that is independent of direct photoresist patterning limitations at small scales.
3Reliability
If peripheral circuit region patterning is performed with conventional methods, then manufacturing is straightforward, but electrical reliability and defect resistance worsen
Solution Approach 1:
The invention applies different patterning approaches to different regions: the first and second patterning steps are selectively applied to the peripheral circuit region while the memory cell region uses a different approach. This local differentiation optimizes electrical reliability for the peripheral circuit region where it is most critical, while maintaining manufacturing feasibility through region-specific process application.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for more precise and reliable patterning, reducing process defects and improving the electrical reliability of semiconductor devices by minimizing ion scattering and maintaining precise line widths.
Implementation Method 1
forming a first photoresist pattern covering at least a part of the second region and exposing the first region of the mask layer structure
Implementation Method 2
etching the mask layer structure by using the first photoresist pattern and the second photoresist pattern
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a mask layer structure on a substrate including a first region and a second region, the mask layer structure covering the first region and the second region of the substrate, forming a first photoresist pattern covering at least part of the second region and exposing the first region of the mask layer structure, forming a second photoresist pattern on the mask layer structure and the first photoresist pattern, and etching the mask layer structure by using the first photoresist pattern and the second photoresist pattern.