Semiconductor Device Fabrication via Segmented Mask Alignment
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Solution Overview
Problem
Conventional interconnection structures in semiconductor manufacturing face performance issues due to alignment errors and leakage caused by the limitations of lithography resolution, leading to poor performance as feature sizes decrease, particularly when forming through holes between grooves.
Innovation Solution
A fabrication method involving the formation of barrier layers on exposed sidewalls, etching a first mask through hole, and using these barrier layers and mask material layers to create grooves and through holes in the to-be-etched layer, ensuring accurate placement and preventing connections between through holes and grooves.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography is used to form through holes and grooves, then manufacturing process is simple, but alignment precision deteriorates due to lithography resolution limitations
Solution Approach 1:
The patent divides the pattern formation into two independent stages: first forming grooves using first mask material layer, then forming through holes using second mask material layer. This segmentation allows each feature to be formed with optimal alignment to the underlying layer, eliminating the cumulative alignment errors that occur when attempting to form both features in a single lithography step. The grooves and through holes are formed separately with their respective masks, ensuring high alignment precision for each feature type.
Solution Approach 2:
The patent performs preliminary actions by first forming the grooves and their associated mask structures before forming the through holes. The first mask material layer is formed, patterned, and used to define grooves completely before the second mask material layer is applied. This preliminary formation of grooves establishes a stable reference structure that ensures subsequent through hole alignment is independent and precise, rather than attempting to align both features simultaneously.
2Area of stationary object
If through holes are formed close to grooves to reduce area, then area is reduced, but leakage occurs due to misalignment and poor separation
Solution Approach 1:
The patent uses separate mask material layers (first and second mask material layers) that are formed at different stages and can be independently optimized. The first mask material layer defines grooves with precise lateral walls, while the second mask material layer defines through holes. This segmentation ensures that even when through holes are positioned close to grooves, the independent mask formation processes maintain proper separation and alignment, preventing electrical leakage while minimizing the overall interconnection structure area.
Solution Approach 2:
The grooves are formed in advance using the first mask material layer, creating well-defined lateral walls that serve as preliminary structures. When the second mask material layer is subsequently formed and patterned to create through holes, the pre-formed groove structures provide stable reference boundaries. This preliminary action ensures that through holes can be positioned close to grooves without compromising electrical isolation, as the groove lateral walls are already established to provide proper separation.
3Productivity
If feature size is reduced to increase integration density, then integration density is improved, but alignment errors increase due to lithography limitations
Solution Approach 1:
The patent segments the patterning process into two independent lithography steps, each optimized for forming specific features at reduced dimensions. The first lithography step forms grooves with the first mask material layer, and the second lithography step forms through holes with the second mask material layer. This segmentation allows each step to be independently optimized for its specific feature size requirements, maintaining alignment precision even as feature dimensions are reduced to increase integration density.
Solution Approach 2:
The patent performs preliminary formation of groove structures before forming through holes. This preliminary action creates stable reference structures that enable subsequent through hole alignment to be performed independently with high precision, even at reduced feature sizes. The pre-formed grooves serve as established boundaries that guide the placement of through holes, maintaining alignment accuracy despite smaller feature dimensions and higher integration density.
Data Source
AI summary
Semiconductor structure and fabrication method are provided. An exemplary method includes: providing a to-be-etched layer; forming a first mask material layer with a barrier region on the to-be-etched layer; forming a first mask groove and a second mask groove separated from each other in the first mask material layer and exposing two sidewalls of the barrier region along an extending direction of the first mask groove; forming barrier layers on exposed sidewalls of the barrier region; forming a first mask through hole in the barrier region of the first mask material layer by etching a portion of the barrier region of the first mask material layer by using the barrier layers as a mask; and forming a first groove, a second groove, and a through hole, by etching the to-be-etched layer using the barrier layers and the first mask material layer as a mask.