Semiconductor Manufacturing Mask Sharing for Capacitance Stability
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Solution Overview
Problem
The manufacturing process of semiconductor elements, particularly MOS type variable-capacitance elements, faces challenges in preventing the deterioration of capacitance characteristics due to impurity implantation, and the high cost associated with the use of multiple masks in photolithography.
Innovation Solution
A method is introduced that forms a first and second implantation barrier layer to prevent impurity implantation into the variable-capacitance element region, while sharing masks to reduce costs, by using these barrier layers to isolate the FET and variable-capacitance element regions during the channel and epitaxy forming processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If masks are shared in different processes to reduce the total number of masks, then manufacturing cost is reduced, but impurities may be implanted into the variable-capacitance element deteriorating its capacitance characteristics
Solution Approach 1:
The patent divides the manufacturing process into separate masking stages: a first masking process for forming the well region, and a second masking process for forming the channel region. This segmentation allows different mask sets to be used for different purposes, preventing impurity contamination while maintaining cost efficiency through mask reuse within each stage.
Solution Approach 2:
The first masking process and well formation are performed before the channel forming process. By establishing the well region structure and protection layers in advance, the patent prevents subsequent impurity implantation from affecting the variable-capacitance element during the channel formation stage.
2Reliability
If multiple masking processes are used to prevent impurity implantation, then capacitance characteristics are preserved, but the total number of masks increases manufacturing cost
Solution Approach 1:
The patent designs mask sets that can serve multiple functions within their respective stages. The first mask set is used for both well region definition and variable-capacitance element protection, while the second mask set handles channel formation and source/drain region definition, reducing the total number of unique masks required.
Solution Approach 2:
The patent implements a mask recovery strategy where mask sets are discarded after completing their specific stage functions and then recovered for reuse in subsequent production batches. This approach reduces the total number of masks needed while maintaining process integrity across multiple manufacturing cycles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively inhibits the deterioration of capacitance characteristics and reduces the number of masks required, thereby saving costs in the semiconductor manufacturing process.
Implementation Method 1
forming a first implantation barrier layer on the surface of the substrate, wherein the first implantation barrier layer covers a surface of a well of a variable-capacitance element region
Implementation Method 2
the first implantation barrier layer is formed by using photomask
Data Source
AI summary
The present disclosure provides a method for manufacturing semiconductor element. The method includes: a first masking process, forming a resist layer on the surface of the substrate; a channel forming process, implanting impurities with the same polarity as a well of an FET region into the surface of the substrate, and forming a channel region for the well of the FET region; a gate forming process, forming gates G respectively on the well of the FET region and the well of the variable-capacitance diode region separated by insulating films; a second masking process, generating a second implantation barrier layer on the surface of the substrate; and an epitaxy forming process, implanting impurities with the opposite polarity to that of the well of the FET region into the surface of the substrate, and forming an epitaxy region for the well of the FET region.