Semiconductor Data Masking Circuit for SSN and ISI Reduction

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Solution Overview

Problem

In semiconductor systems, the increased number of data bits with phase changes during transmission leads to frequent occurrences of simultaneous switching noise (SSN) and inter-symbol interference (ISI) phenomena, which are not effectively mitigated by existing technologies.

Innovation Solution

A semiconductor device with a data detection circuit that identifies bits with a predetermined logic level and generates a detection signal, coupled with a selection/transmission circuit and a masking signal generation circuit to control data masking and bus inversion operations, thereby reducing noise and interference.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of data bits with phase changes increases during transmission, then data transmission capacity increases, but simultaneous switching noise (SSN) and inter-symbol interference (ISI) phenomena occur more frequently

Engineering Contradiction:
Improvenumber of data bitsVSAvoidSSN and ISI phenomena
Core Design Contradiction:
Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary action by detecting the number of bits with predetermined logic levels before data transmission and generating masking signals in advance. The data detection circuit counts bits with specific logic levels (e.g., logic 0 or logic 1) before transmission, and based on this detection, masking signals are generated to prevent SSN and ISI phenomena during transmission. This preliminary detection and signal generation resolves the contradiction by preparing mitigation measures before the harmful effects can occur.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by using detection signals from the data detection circuit to control the generation of masking signals. The system continuously monitors the data bit composition and adjusts masking signal generation accordingly. When the detection circuit identifies a high number of bits with predetermined logic levels that could cause SSN or ISI, the feedback mechanism triggers appropriate masking operations to suppress these phenomena, thus resolving the contradiction between transmission capacity and noise/interference.

Inventive Principle:
Principle #23Feedback

2Manufacturing precision

If data masking operation is performed to store only desired bits, then data storage precision improves, but device complexity increases due to additional masking signal generation

Engineering Contradiction:
Improvedata storage precisionVSAvoidmasking signal generation circuit
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies universality by designing the data detection circuit and masking signal generation circuit to handle multiple data bit patterns and logic level combinations. The detection circuit can identify different numbers of bits with predetermined logic levels, and the masking signal generation circuit can produce various masking signal patterns based on detection results. This multi-functional design achieves precise data storage while managing complexity through unified circuit architecture rather than separate circuits for each masking scenario.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent uses parameter changes by varying the masking signal generation based on detected data bit parameters. When the detection circuit identifies specific patterns (e.g., too many logic 0s or logic 1s), the system changes masking signal parameters (such as enabling/disabling masking, or changing masking patterns) to optimize storage precision. This dynamic parameter adjustment achieves high storage precision only when needed, reducing the effective complexity compared to always-active complex masking systems.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS10535380B1Semiconductor devices and semiconductor systems including the semiconductor devices
Publication Date: 2020.01.14 SK HYNIX INC
  • US10535380B1 patent drawing
  • US10535380B1 patent drawing
  • US10535380B1 patent drawing

AI summary

A semiconductor device includes a data detection circuit configured to detect a number of bits having a predetermined logic level among bits included in data to generate a detection signal. The semiconductor device also includes a selection/transmission circuit configured to output the detection signal or a control data signal as a pre-masking signal based on a selection/transmission signal. The semiconductor device further includes a masking signal generation circuit configured to latch the pre-masking signal based on a pipe input control signal and configured to output the latched signal of the pre-masking signal as a masking signal for controlling a data masking operation based on a pipe output control signal.