Semiconductor Memory Device 3T Configuration Area Reduction
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Solution Overview
Problem
Two-transistors/one-capacitor (2T/1C) semiconductor memory devices require frequent refresh operations due to their dynamic nature, leading to complex controller circuits and high power dissipation, and the need for large capacitors increases occupied area and decreases integration levels.
Innovation Solution
A semiconductor memory device with a 3T configuration using a memory transistor and two control transistors, where the memory transistor exhibits gate-controlled memory characteristics, eliminating the need for a capacitor and allowing data storage through oxide heterojunction field effect transistors, which reduces occupied area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If a capacitor is used in 2T/1C memory cell to store data, then data retention time is extended, but occupied area increases and integration level decreases
Solution Approach 1:
The patent extracts and removes the capacitor component from the memory cell structure. Instead of using a capacitor to store data charges, the invention uses a single transistor whose gate voltage state directly represents the stored data, eliminating the need for capacitive storage elements and their associated area requirements.
Solution Approach 2:
The patent changes the fundamental storage parameter from charge storage in a capacitor to voltage state storage in a transistor gate. The memory cell stores data by maintaining different voltage levels on the transistor gate, transforming the storage mechanism from capacitive charge retention to transistor state retention.
2Duration of action of stationary object
If capacitor refresh operations are performed periodically in 2T/1C memory, then data retention is maintained, but power dissipation increases and controller circuit complexity increases
Solution Approach 1:
The patent removes the periodic refresh operation requirement by eliminating the capacitor-based storage mechanism that necessitates refresh. The transistor-based storage naturally maintains its state without requiring periodic rewriting, thereby removing the energy-consuming refresh controller circuitry.
Solution Approach 2:
The memory transistor inherently maintains its stored data state through its own physical properties without requiring external refresh operations. The transistor's gate voltage state is self-maintaining within the operational range, providing automatic data retention without additional control circuits.
3Duration of action of stationary object
If large capacitance is used in memory cell to extend retention time, then data retention time increases, but occupied area increases
Solution Approach 1:
The patent extracts the capacitor element entirely from the memory cell, replacing capacitive storage with transistor-based voltage state storage. This eliminates the direct relationship between retention time and capacitance size, as retention is now determined by transistor characteristics rather than capacitor size.
Data Source
AI summary
A semiconductor memory device and a method for accessing the same are disclosed. The semiconductor memory device comprises a memory transistor, a first control transistor and a second control transistor, wherein a source electrode and a gate electrode of the first control transistor are coupled to a first bit line and a first word line respectively, a drain electrode and a gate electrode of the second control transistor are coupled to a second word line and a second bit line respectively, a gate electrode of the memory transistor is coupled to a drain electrode of the first control transistor, a drain electrode of the memory transistor is coupled to a source electrode of the second control transistor, and a source electrode of the memory transistor is coupled to ground, and wherein the memory transistor exhibits a gate electrode-controlled memory characteristic. The semiconductor memory device increases integration level and decreases refresh frequency.