Semiconductor Memory Device Adaptive Read Operation
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Solution Overview
Problem
Semiconductor memory devices face inefficiencies in determining whether memory cells store single or multiple bits, leading to increased size and performance degradation due to the need for flag cells to manage bit storage.
Innovation Solution
A method involving pre-reading selected memory cells using a pre-read voltage to determine if they store single or multiple bits, allowing for adaptive main reading operations without flag cells, thereby reducing device size and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flag cells are used to manage bit storage information, then the reliability of determining single or multiple bit storage is improved, but the device area increases
Solution Approach 1:
The patent extracts and eliminates the flag cell component from the memory device. Instead of using dedicated flag cells to store bit storage information, the invention uses the existing memory cells themselves to indicate whether they store single or multiple bits through their threshold voltage characteristics, thereby removing the extra hardware overhead while maintaining the necessary information.
Solution Approach 2:
The patent makes the memory cells serve multiple functions: they both store data bits and indicate their storage mode (single or multiple bits) through threshold voltage levels. The same memory cell structure is used for both data storage and status indication, eliminating the need for separate flag cells and improving area efficiency.
2Measurement precision
If flag cells are used to manage bit storage, then the accuracy of reading operations is improved, but the device complexity increases
Solution Approach 1:
The patent removes the flag cell infrastructure from the device architecture. The determination of whether memory cells store single or multiple bits is achieved by reading threshold voltage information directly from the memory cells during normal read operations, without requiring separate flag cell read mechanisms, thus simplifying the device while maintaining reading accuracy.
Solution Approach 2:
The read operation is enhanced to serve dual purposes: it both retrieves stored data and determines the bit storage mode by analyzing threshold voltage characteristics. This multi-functional read operation eliminates the need for separate flag cell management circuits, reducing device complexity while preserving reading accuracy.
3Productivity
If adaptive main reading is performed based on pre-reading, then the productivity of read operations is improved, but the use of energy increases
Solution Approach 1:
The patent performs a preliminary pre-read operation to determine the bit storage mode (single or multiple bits) before executing the main read operation. This preliminary action allows the system to adaptively select the appropriate read strategy, improving overall productivity by avoiding unnecessary full read operations while the energy cost is offset by the efficiency gains from targeted reading.
Solution Approach 2:
The patent implements dynamic read operations where the main reading strategy adapts based on the pre-read results. When multiple bits are detected, a comprehensive read is performed; when single bits are detected, a simplified read is used. This dynamic adaptation optimizes productivity by matching the read operation intensity to the actual data requirements, with energy consumption justified by the significant productivity improvements.
Data Source
AI summary
A method includes performing a pre-reading on memory cells selected from a plurality of memory cells according to a pre-read voltage and determining whether the selected memory cells each are read as a first logical value or a second logical value, comparing a number of memory cells read as the first logical value among the selected memory cells with a predetermined number, and when the number of selected memory cells read as the first logical value is smaller than the predetermined number, performing a first main reading of the selected memory cells, the first main reading adapted to read a memory cell that stores multiple bits.