Semiconductor Memory Address Decoding Circuit for Defective Cell Handling
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Solution Overview
Problem
Semiconductor memory units with defective cells are often discarded, leading to increased fabrication costs due to the need for different processes for various memory capacities, and existing redundancy and error correction techniques are insufficient to address this issue effectively.
Innovation Solution
A semiconductor memory and address-decoding circuit that allows operation by disabling a predetermined portion of the memory, using a switching circuit and global address-setting code to convert external addresses into internal addresses, enabling the selection of memory units and reducing capacity without affecting the original access function.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If semiconductor memory units with defective cells are discarded, then product quality is maintained, but fabrication cost increases due to lower yield
Solution Approach 1:
The patent changes the operational parameters of the memory by using address-decoding circuits to modify how addresses are interpreted. By altering the address decoding behavior through control signals, defective memory regions are excluded from operation while valid regions continue to function, thereby maintaining product quality without discarding the entire memory unit
Solution Approach 2:
The memory is segmented into multiple regions through the address-decoding circuit, which divides the address space into valid and invalid portions. This segmentation allows the system to operate only on healthy memory regions while isolating defective areas, thus preserving overall memory functionality and improving yield
2Adaptability or versatility
If different fabrication processes are used for different memory capacities, then specific capacity requirements are met, but fabrication cost and complexity increase
Solution Approach 1:
The patent implements a universal address-decoding circuit that can configure the same memory device to operate at different effective capacities. By controlling the decoding logic, a single memory chip can be adapted to provide various capacity levels (e.g., 4Mb, 8Mb, 16Mb) without requiring different fabrication processes, thereby simplifying manufacturing while maintaining capacity flexibility
Solution Approach 2:
The memory system dynamically adjusts its effective capacity through controllable address-decoding circuits. The decoding behavior can be modified via control signals or configuration bits, allowing the same physical memory to present different logical capacities to the user, thus achieving capacity adaptability without process changes
3Productivity
If redundancy technique and error correction code technique are used, then product yield increases, but device complexity and fabrication cost increase
Solution Approach 1:
Instead of adding complex redundancy and error correction circuits to handle defective cells, the patent extracts or removes the problematic defective regions from the addressable space through address-decoding control. By excluding defective areas from operation rather than attempting to correct or replace them, the solution achieves high yield without increasing circuit complexity
Data Source
AI summary
A semiconductor memory and address-decoding circuit and method for decoding address allow the semiconductor memory to operate under a decreased capacity by disabling or hiding a predetermined portion of the semiconductor memory. The semiconductor memory has a first address-inputting circuit configured to receive a first external address, a switching circuit configured to switch a predetermined portion of the first external address to form an internal address, at least one address-setting code configured to set at least one predetermined bit of the internal address, a decoder coupling to the switching circuit and the address-setting code, and a memory array coupling to the decoder, wherein the decoder is configured to select at least one memory unit of the memory array based on the internal address. The first address-inputting circuit, the switching circuit and the address-setting code can be considered as an address-decoding circuit.