Semiconductor Memory Device Air Gap Tunnel Layer
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Solution Overview
Problem
The U-shaped three-dimensionally stacked memory faces issues with cell characteristic variations due to differing structures on either side of the lowermost control gate and increased leakage from the charge storage layer, particularly when scaling down, which affects charge retention.
Innovation Solution
The lowermost control gate is used as a dummy gate, and a sacrificial metal layer is filled in the lower portion of the tunnel layer to support the U-shaped silicon pillar and core layer, while an air gap layer is used as the tunnel layer to reduce leakage and improve charge retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the lowermost control gate is used as a functional gate, then the memory can operate, but cell characteristic variations increase due to different structures on either side of the gate
Solution Approach 1:
The lowermost control gate is designed as a dummy gate that is removed after serving its temporary purpose of supporting the U-shaped silicon pillar during manufacturing. This disposable approach allows the gate to provide structural support during fabrication without causing cell characteristic variations in the final device, as it is removed before operation.
Solution Approach 2:
The lowermost control gate is formed as a dummy gate in advance during the manufacturing process to provide structural support for forming the U-shaped silicon pillar. This preliminary action enables proper pillar formation, after which the dummy gate is removed, ensuring uniform cell characteristics without the complications of an asymmetric functional gate structure.
2Productivity
If the memory is scaled down to reduce cell size, then higher integration is achieved, but leakage from the charge storage layer increases
Solution Approach 1:
A tunnel layer is introduced as an intermediary between the charge storage layer and the U-shaped silicon pillar. This tunnel layer acts as a mediator that reduces direct leakage paths while allowing the scaled-down structure to maintain proper electrical characteristics, thus enabling higher integration without proportionally increasing leakage.
3Productivity
If a U-shaped silicon pillar is used to form memory strings, then three-dimensional stacking is achieved, but the structure requires precise alignment and control
Solution Approach 1:
The lowermost control gate is used as a temporary sacrificial structure during manufacturing. It provides a reference and support structure that enables precise formation of the U-shaped silicon pillar, after which it is removed. This disposable template approach simplifies the manufacturing process and reduces the precision requirements for direct pillar alignment.
Data Source
AI summary
According to one embodiment, a semiconductor memory device comprises a first layer, a first conductive layer, a insulating layer, and a second conductive layer stacked on a substrate, a block insulating layer on inner surfaces of a pair of through-holes formed in the first conductive layer, the insulating layer, and the second conductive layer, and on an inner surface of a connecting hole connecting lower ends of the pair of through-holes, a charge storage layer on the block insulating layer, a second layer on the charge storage layer, and a semiconductor layer on the second layer. The second layer includes an air gap layer on the charge storage layer in the pair of through-holes, and a third conductive layer on the charge storage layer in the connecting hole.