3D Semiconductor Memory Integration via Air Gaps and Vertical Channels
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Solution Overview
Problem
The integration density of semiconductor devices is limited in two-dimensional designs, leading to increased manufacturing costs and challenges in scaling down while maintaining performance, necessitating the development of three-dimensional arrays to enhance integration density and operational speed.
Innovation Solution
A method of fabricating semiconductor memory devices involving the formation of a mold stack with alternating sacrificial layers, creating vertical channels, patterning to form word line cuts, and removing sacrificial layers to form recessed regions, gates, and air gaps, which are then insulated, allowing for the reduction of parasitic capacitance and improved integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If two-dimensional design is used for semiconductor devices, then manufacturing process is simpler, but integration density is limited
Solution Approach 1:
The patent transitions from two-dimensional planar structures to three-dimensional vertical structures by forming vertical channels that extend through multiple layers of sacrificial materials and insulation layers. This dimensional change enables significantly higher integration density by utilizing the vertical space above the substrate rather than only the horizontal plane.
2Quantity of substance
If integration density is increased through scaling down, then more devices fit in same area, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the structure into multiple discrete layers including alternating sacrificial layers (first and second sacrificial layers) and insulation layers. Each layer can be formed and patterned independently, allowing for precise control of dimensions and alignment. The vertical channels are formed by selectively removing specific sacrificial layers, enabling precise positioning without requiring extremely tight tolerances across the entire structure.
Solution Approach 2:
The patent uses sacrificial layers as intermediary structures that facilitate the formation of vertical channels and air gaps. These sacrificial layers are deposited and patterned with standard precision, then selectively removed to create the final high-precision vertical features. This intermediary approach allows standard manufacturing processes to achieve high precision results without requiring advanced lithography.
3Quantity of substance
If three-dimensional array is formed to enhance integration density, then operational speed improves, but device complexity increases
Solution Approach 1:
The patent combines multiple functions into the vertical channel structure: the vertical channels serve as both the structural framework for high-density integration and as the conductive pathways for signal transmission. The air gaps formed by removing sacrificial layers simultaneously provide electrical isolation between adjacent structures and reduce parasitic capacitance, improving operational speed. This merging of structural and functional elements achieves high integration density without proportionally increasing device complexity.
Data Source
AI summary
A method of fabricating a semiconductor memory device includes forming a mold stack on a substrate and the mold stack including first sacrificial layers and second sacrificial layers alternately stacked on the substrate. The method also includes forming a plurality of vertical channels that penetrate the mold stack and that contact the substrate, patterning the mold stack to form word line cuts between the vertical channels, the word line cuts exposing the substrate, removing one of the first and second sacrificial layers to form recessed regions in the mold stack, forming a data storage layer, at least a portion of the data storage layer being formed between the vertical channels and the gates, forming gates in the recessed regions, forming air gaps between the gates by removing the other of the first and second sacrificial layers, and forming an insulation layer pattern in the word line cuts.