3D Semiconductor Memory Device With Alternating Channel Column Shapes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving a stable structure with increased integration while minimizing structural instability and operational deterioration, particularly due to the increased occupation area of row decoders and package fit-in issues.
Innovation Solution
The semiconductor memory device incorporates a three-dimensional structure with alternately arranged channel columns having different uppermost plane shapes, such as circular and elliptical shapes, to reduce memory block size and occupation area, thereby enhancing integration and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration is increased to satisfy consumer demand for high performance and low cost, then productivity and cost-effectiveness are improved, but structural instability and operational deterioration occur
Solution Approach 1:
The patent transitions from two-dimensional planar memory structures to three-dimensional vertically stacked structures. Multiple gate conductive films are stacked in the third dimension (vertical direction) above the substrate, with channel columns extending through the stacked structure. This dimensional change enables significantly higher integration density while maintaining structural stability through the alternating pattern of different-shaped columns that distribute mechanical stress.
Solution Approach 2:
The patent employs alternating first columns with uppermost planes having a first shape (e.g., circular cross-section) and second columns with uppermost planes having a second shape (e.g., elliptical or rectangular cross-section). This asymmetric alternation creates a stable structural pattern that prevents uniform stress distribution issues while maximizing space utilization in the three-dimensional electrode structure.
2Area of moving object
If more memory cells are integrated into a smaller area, then chip size is reduced, but package fit-in issues arise due to structural constraints
Solution Approach 1:
By stacking gate conductive films and channel columns in the vertical dimension rather than expanding horizontally, the patent achieves higher integration density within the same footprint. This allows the memory device to fit within standard package dimensions while maintaining high capacity, as the electrode structure extends primarily in the vertical direction rather than requiring larger lateral area.
Solution Approach 2:
The patent applies different cross-sectional shapes (first shape and second shape) to alternating columns at different locations within the electrode structure. This local variation optimizes space utilization in specific regions while maintaining overall structural integrity, allowing the device to adapt to package constraints without compromising integration density.
3Area of stationary object
If channel columns with different uppermost plane shapes are alternately arranged, then memory block size and occupation area are reduced, but manufacturing complexity increases
Solution Approach 1:
The patent divides the channel column array into alternating segments of first columns and second columns, where each segment type has a consistent uppermost plane shape. This segmentation into repeating units simplifies the manufacturing process, as each column type can be formed using standardized processes, and the alternating pattern creates a predictable, modular structure that reduces overall complexity despite the variety of shapes.
Solution Approach 2:
The patent varies the cross-sectional shape parameter (first shape vs. second shape) of channel columns while maintaining consistent dimensional relationships and spacing. This controlled parameter variation allows optimization of memory block size and packing density without requiring fundamentally different manufacturing processes for each column type, thus managing complexity while achieving area reduction.
Data Source
AI summary
A semiconductor memory device includes an electrode structure including a plurality of gate conductive films stacked on a substrate and a channel array in which a plurality of channel columns passing through the electrode structure are arranged in a second direction. The plurality of channel columns may include a first column whose uppermost plane has a first shape and a second column whose uppermost plane has a second shape. N (N is a natural number equal to more than 1) first columns and N second columns are alternately arranged in a first direction different from the second direction.