Semiconductor Memory Array Noise Reduction via Segmented Mats
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Solution Overview
Problem
Existing semiconductor integrated circuit devices face a trade-off between achieving small memory cell array size and excellent noise characteristics, with open bit line layouts being weak against noise and folded bit line layouts resulting in larger arrays despite better noise cancellation.
Innovation Solution
A semiconductor integrated circuit device with a memory array layout where memory cells, each comprising two transistors and one storage element, are disposed at all intersections between bit lines and word lines, employing a folded bit line layout to achieve both small size and improved noise characteristics by using sense amplifiers with bit line pairs in the same mat and activating corresponding word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If open bit line layout is used, then memory cell array size is reduced, but noise characteristics deteriorate
Solution Approach 1:
The memory cell array is divided into multiple mats, with each mat containing a folded bit line layout. This segmentation allows each mat to benefit from noise cancellation while the overall array maintains compact size through efficient packing of multiple mats together.
Solution Approach 2:
Multiple mats are combined to form the complete memory cell array. Each mat independently provides noise cancellation through its folded bit line structure, and the combination of mats achieves both noise immunity and space efficiency.
2Object-affected harmful factors
If folded bit line layout is used, then noise characteristics are improved, but memory cell array size increases
Solution Approach 1:
The memory cell array is divided into multiple mats, with each mat containing a folded bit line layout. This segmentation allows each mat to benefit from noise cancellation while the overall array maintains compact size through efficient packing of multiple mats together.
Solution Approach 2:
The memory cell array is extended in the column direction by adding multiple mats, allowing the array to achieve the required storage capacity without increasing the row direction footprint. This dimensional expansion enables compact overall layout while maintaining folded bit line noise cancellation in each mat.
Data Source
AI summary
A memory device including memory cells each have two transistors and one storage element connected in series in this order between a corresponding one of bit lines and a constant voltage. The two transistors respectively have gate electrodes respectively connected to a corresponding one of first word lines and a corresponding one of second word lines. A memory array includes mats each having the memory cells disposed at all intersections between the bit lines and the first word lines, sense amplifiers each input with a corresponding pair of the bit lines in the same mat as a bit line pair, and first and second word drivers adapted to activate the first and second word lines, respectively.