Semiconductor Memory Array With Dual-Switch Signed-Data Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing computing-in-memory (CIM) systems require complex systems software and multiple cycles to perform large-scale calculations, especially for binary input data and weights, leading to inefficiencies in processing time and power consumption.
Innovation Solution
A semiconductor device with a memory array using resistive random-access memory (ReRAM) or magnetoresistive random-access memory (MRAM) that incorporates memory cells with two switches to process data values of +1 and -1 simultaneously, reducing the need for additional cycles and power-saving operations by adjusting voltage levels based on data values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing CIM systems use complex systems software and multiple cycles for large-scale calculations, then calculation accuracy is maintained, but processing time and power consumption increase
Solution Approach 1:
The patent replaces traditional mechanical computing systems with complex software and multiple processing cycles with a direct physical computation system. Memory cells with two switches directly perform calculations through electrical signal operations, substituting the mechanical/software-based approach with an electrical/physical mechanism that inherently performs computations during memory operations.
Solution Approach 2:
The memory cells are designed to perform multiple functions: they store data and simultaneously perform calculations. The two-switch configuration enables the same memory infrastructure to handle both positive and negative data values, perform arithmetic operations, and maintain storage functionality, eliminating the need for separate processing units and software layers.
2Productivity
If existing CIM systems process binary input data and weights using multiple cycles, then calculation accuracy is maintained, but operation time increases
Solution Approach 1:
The patent enables continuous computation by processing both positive and negative data values simultaneously within the same operation cycle. The two-switch memory cell configuration allows uninterrupted calculation flow without requiring alternating cycles for different data types, maintaining continuous useful action throughout the computation process.
Solution Approach 2:
The memory cells are pre-configured with two switches that are ready to handle both positive and negative values simultaneously. This preliminary preparation of the computational infrastructure eliminates the need for sequential processing and preliminary setup cycles, allowing immediate simultaneous computation of all data values.
3Loss of energy
If existing CIM systems use additional cycles for power-saving operations, then energy efficiency is improved, but processing throughput decreases
Solution Approach 1:
The memory cells perform computations using their own stored data and internal switches without requiring external processing cycles or additional power management interventions. The system serves its own computational needs through the inherent functionality of the two-switch memory cells, eliminating the need for separate power-saving cycles that would reduce throughput.
4Productivity
If memory cells process positive and negative data values separately in existing CIM systems, then computational accuracy is maintained, but processing efficiency decreases
Solution Approach 1:
The patent merges the processing of positive and negative data values into a single simultaneous operation. The two-switch memory cell configuration combines what were previously separate processing streams into one unified computational event, maintaining accuracy through the precise electrical characteristics of the switches while dramatically improving processing efficiency.
Data Source
AI summary
A semiconductor device includes a memory array. The memory array is configured to calculate first data and second data, and includes a first memory cell and a second memory cell. The first memory cell is configured to generate a first current signal at a first node, in response to the first data. The second memory cell is configured to generate a second current signal at the first node when the first memory cell generating the first current signal, in response to the second data. When the first data has a first data value and the second data has a second data value, the second memory cell is further configured cancel the first current signal with the second current signal. The second data value is a negative value of the first data value.