Semiconductor Memory Array Segmentation for Voltage Stability
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Solution Overview
Problem
Existing semiconductor devices face instability when simultaneously writing or reading data from multiple non-volatile memory cells due to excessive current flowing through bit lines and diffusion source lines, leading to potential voltage drops and rises that affect data access operations.
Innovation Solution
The semiconductor device incorporates a configuration where the number of active cells is less than the cross sections of bit lines and word lines, with dummy cells at unused intersections, reducing current flow through bit lines and diffusion source lines, and using metal source lines between bit lines to manage current load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple active cells are connected to a single bit line or word line for simultaneous data access, then data access speed is improved, but current density increases causing voltage instability
Solution Approach 1:
The patent divides the cell array into multiple blocks, each with its own dedicated bit line and word line. This segmentation allows simultaneous access to multiple cells across different blocks without concentrating excessive current on a single bit line or word line, thus maintaining both high data access speed and voltage stability.
Solution Approach 2:
The patent introduces a block dimension to the memory architecture, organizing cells into a three-dimensional hierarchy (blocks × bit lines × word lines). This dimensional expansion enables parallel access to multiple cells distributed across different blocks, reducing current density on individual bit lines and word lines while maintaining high throughput.
2Quantity of substance
If the number of active cells equals the number of cross sections for maximum storage density, then memory capacity is improved, but current flow becomes excessive causing operation instability
Solution Approach 1:
By dividing the memory into multiple blocks with dedicated bit lines and word lines, the patent enables full utilization of cross sections across all blocks while distributing the current load. This segmentation allows maximum memory capacity without excessive current concentration on any single line.
Solution Approach 2:
The patent combines multiple block structures into a unified memory system where each block contributes to overall capacity. The merged system achieves high memory capacity by aggregating cells across blocks while maintaining operational stability through distributed current paths.
Data Source
AI summary
A semiconductor device has a plurality of bit lines BL provided in a memory cell area 101, a plurality of word lines WL provided crossing the plurality of bit lines BL, a plurality of diffusion source lines VSL provided along the plurality of word lines WL, a plurality of non-volatile active cells AC storing data, the plurality of non-volatile active cells AC being provided at cross sections of the plurality of bit lines BL and the plurality of word lines WL and being connected to the plurality of bit lines BL, the plurality of word lines WL, and the plurality of diffusion source lines VSL, and a controller simultaneously writes or reads data to and from at least two active cells AC among the plurality of active cells AC, in which the number of the plurality of active cells AC is less than that of the cross sections.