Semiconductor Memory Array Segmentation for Data Reliability
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Solution Overview
Problem
The reliability of data stored in flash memory cells is degraded due to variations in threshold voltage, especially when the gaps between memory cells are narrowed to increase integration density, leading to potential errors in read operations.
Innovation Solution
A semiconductor device with a memory array organized into sub-block and main block groups, featuring an operation circuit that performs read and test read operations, and counts the number of read operations for each word line, allowing for targeted test read operations on sub-block groups with higher operation counts, thereby improving data preservation characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If gaps between memory cells are narrowed to increase integration density, then integration density is improved, but threshold voltage variation increases leading to degraded data reliability
Solution Approach 1:
The memory array is divided into multiple sub-block groups, which are further divided into main block groups. This segmentation allows selective testing and management of different memory regions, enabling targeted reliability improvement without affecting the entire array's integration density.
Solution Approach 2:
Test read operations are performed preliminarily on sub-block groups before normal read operations. By counting read operation frequencies and identifying sub-block groups with high operation counts, the system proactively detects potential threshold voltage variations before they cause data errors.
2Speed
If read operations are performed frequently on memory cells, then data access speed is improved, but threshold voltage variation increases leading to degraded data preservation characteristics
Solution Approach 1:
The operation circuit counts the number of read operations for each sub-block group and uses this feedback information to determine when to perform test read operations. When the read operation count exceeds a reference value, test read operations are triggered to detect and correct potential errors, creating a closed-loop system that balances access speed with data preservation.
Solution Approach 2:
The system changes operational parameters by switching between normal read operations and test read operations based on the read operation count. This parameter change allows the system to maintain high data access speed during normal operation while periodically verifying data integrity when thresholds are exceeded.
Data Source
AI summary
A semiconductor device includes a memory array including a plurality of memory blocks, wherein the memory blocks are grouped into sub-block groups, and the sub-block groups are grouped into main block groups; an operation circuit suitable for performing a read operation and a test read operation on memory cells included in the memory block; and a read counter suitable for counting a first number of read operations for each word line in the respective main block groups and a second number of read operations for the respective sub-block groups.