Semiconductor Memory Backup Sub-Blocks for Power-Loss Recovery

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Solution Overview

Problem

Existing semiconductor memory devices face challenges in ensuring data reliability during program operations, particularly due to sudden power losses that can result in data loss.

Innovation Solution

The semiconductor memory device incorporates a memory block structure with both normal and backup sub-blocks, where normal data is programmed to a normal sub-block and parity data is programmed to a backup sub-block, with a backup controller managing data transfer to the backup block in case of power failures.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If normal data is programmed only to a normal sub-block without backup, then program operation speed is maintained, but data reliability deteriorates due to sudden power losses

Engineering Contradiction:
Improvedata reliabilityVSAvoidmemory block structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The memory block is divided into multiple sub-blocks with different functions: normal sub-blocks for storing normal data and a dedicated backup sub-block for storing backup data. This segmentation allows the system to maintain data reliability through redundancy while preserving program operation speed by keeping the backup mechanism structurally integrated rather than adding external backup systems.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The backup sub-block is prepared in advance within the same memory block structure, and backup data is automatically programmed to the backup sub-block during the normal program operation. This preliminary action ensures that backup capacity is ready before power loss occurs, eliminating the need for post-failure recovery operations and maintaining program speed.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If backup data is programmed to a separate backup block, then data integrity is improved, but program operation time increases

Engineering Contradiction:
Improvedata integrityVSAvoidprogram operation time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The backup sub-block is merged into the same memory block structure as the normal sub-blocks, sharing the same peripheral circuit and control logic. This merging allows backup data to be programmed simultaneously with normal data during the same program operation, eliminating the need for separate backup operations and preventing additional time loss.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The program operation continues uninterrupted to program both normal data to normal sub-blocks and backup data to the backup sub-block simultaneously. This continuous action ensures that data integrity is maintained through redundant storage without pausing or extending the program operation time.

Inventive Principle:
Principle #20Continuity of useful action

3Reliability

If parity data is stored in the backup block, then data recovery capability is enhanced, but storage capacity for normal data is reduced

Engineering Contradiction:
Improvedata recovery capabilityVSAvoidstorage capacity
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

Different sub-blocks within the memory block are assigned different qualities and functions: normal sub-blocks are optimized for storing normal data with full capacity, while the backup sub-block is dedicated to storing backup data. This local quality differentiation ensures that each sub-block serves its specific purpose efficiently, with the backup sub-block providing targeted data recovery capability without reducing the storage capacity of normal sub-blocks.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12386520B2Semiconductor memory device and operating method of the semiconductor memory device
Publication Date: 2025.08.12 SK HYNIX INC
  • US12386520B2 patent drawing
  • US12386520B2 patent drawing
  • US12386520B2 patent drawing

AI summary

A semiconductor memory device and a method of operating the semiconductor memory device are provided. The semiconductor memory device includes a memory block including a plurality of sub-blocks, a peripheral circuit configured to perform a program operation on the memory block, and control logic configured to control the peripheral circuit to perform the program operation on the memory block, wherein the program operation comprises programming to program normal data to a first sub-block, allocated to be a normal sub-block, among the plurality of sub-blocks, and programming parity data of the normal data to a second sub-block, allocated to be a backup block, among the plurality of sub-blocks.