Semiconductor Memory Device With Embedded Composite Bit Line
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Solution Overview
Problem
The miniaturization of transistors in semiconductor devices leads to short-channel effects, and embedding bit lines into the substrate to reduce resistance is challenging due to high resistance in diffusion layer wiring, hindering high-speed operation.
Innovation Solution
A semiconductor memory device with a vertical transistor using a silicon pillar, where a bit line is embedded in the substrate with both a silicon material region and a low-resistance region, and a memory element is connected to the diffusion layers, reducing bit line resistance and preventing substrate pollution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bit line is formed using diffusion layer to embed in substrate, then bit line can be embedded into substrate, but the wiring has high resistance and prevents high-speed operation
Solution Approach 1:
The bit line is constructed as a composite structure with a first bit line portion made of diffusion layer and a second bit line portion made of silicide layer. This composite material approach combines the embedding capability of diffusion layer with the low resistance property of silicide, resolving the contradiction between embeddability and resistance.
Solution Approach 2:
The invention changes the material parameter of the bit line from pure diffusion layer to a combination of diffusion layer and silicide layer. By introducing silicide material with lower resistance, the bit line's electrical resistance parameter is improved while maintaining the embedding capability.
2Productivity
If transistors are miniaturized to increase integration, then device integration is improved, but short-channel effect occurs and device cannot operate correctly
Solution Approach 1:
The invention transitions from planar transistor configuration to three-dimensional FinFET structure. By extending the channel in the vertical dimension (forming fins perpendicular to the substrate), the device achieves higher integration density while maintaining proper operation through enhanced gate control in the third dimension.
Solution Approach 2:
The gate electrode wraps around the fin structure in a nested configuration, with the gate surrounding the channel region. This nested geometry provides superior gate control over the channel, preventing short-channel effects while enabling miniaturization and high integration.
3Loss of energy
If low-resistance material is used for bit line, then bit line resistance is reduced, but substrate may be polluted
Solution Approach 1:
The diffusion layer serves as an intermediary between the silicide bit line portion and the substrate. This intermediate layer prevents direct contact between the silicide material and the substrate, reducing bit line resistance while preventing substrate pollution from the low-resistance material.
Data Source
AI summary
A semiconductor memory device includes a silicon pillar, a gate electrode covering a side surface of the silicon pillar via a gate insulation film, diffusion layers (11, 12) provided in a lower part and an upper part, respectively of the silicon pillar, a bit line connected to the diffusion layer (11), and a memory element connected to the diffusion layer (12). The bit line includes a silicon material region in contact with the diffusion layer (11), and a low-resistance region including a material having lower electric resistance than that of the silicon material region. As a result, the resistance of the bit line embedded in the substrate can be decreased.