Semiconductor Memory Device Bit Line Segmentation
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Solution Overview
Problem
Current semiconductor memory devices face challenges in shortening write time, read time, reducing circuit area, and minimizing power consumption due to high load capacitance, precharged bit lines, and unnecessary charge/discharge events.
Innovation Solution
The semiconductor memory device incorporates a configuration with multiple local and global bit lines, write transistors, and a precharge circuit, allowing for simultaneous control of write transistors and independent operation of read circuits to reduce load capacitance and power consumption, enabling faster write and read operations without unnecessary charge/discharge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If bit lines are hierarchically divided into local and global bit lines with transfer transistors, then load capacitance is reduced, but write time increases due to setup time requirements
Solution Approach 1:
The patent applies dynamics by making the connection between local and global bit lines dynamic rather than static. Transfer transistors are used to dynamically connect local bit lines to global bit lines only when needed, rather than having permanent connections. This allows the system to reduce capacitance when connections are not active while enabling fast write operations when connections are established.
Solution Approach 2:
The patent applies preliminary action by precharging global bit lines to appropriate voltage levels before write operations begin. This precharging ensures that when transfer transistors are activated, the voltage levels are already optimized for fast writing, eliminating the need to wait for voltage stabilization during the write operation.
2Reliability
If global bit lines are precharged to high level before write operations, then write stability is improved, but write time increases due to waiting for voltage levels to be fixed
Solution Approach 1:
The patent applies preliminary action by precharging global bit lines to appropriate voltage levels before write operations begin. This precharging ensures that when transfer transistors are activated, the voltage levels are already optimized for fast writing, eliminating the need to wait for voltage stabilization during the write operation.
Solution Approach 2:
The patent uses transfer transistors as intermediaries between local and global bit lines. These transistors are controlled to connect local bit lines to global bit lines at precisely the right moment, allowing the system to maintain stability through controlled connections while minimizing the time voltage levels need to be held in intermediate states.
3Reliability
If write control signal timing is delayed to wait for global bit line voltage levels, then write stability is improved, but overall cycle time increases
Solution Approach 1:
The patent applies preliminary action by precharging global bit lines to appropriate voltage levels before write operations begin. This precharging ensures that when transfer transistors are activated, the voltage levels are already optimized for fast writing, eliminating the need to wait for voltage stabilization during the write operation.
Solution Approach 2:
The patent maintains continuity of useful action by overlapping the precharging of global bit lines with the preparation of write data. These operations occur simultaneously rather than sequentially, ensuring that no time is wasted and that the system continuously performs useful work throughout the write cycle.
4Quantity of substance
If local bit lines are connected to global bit lines through transfer transistors, then load capacitance is reduced, but circuit area increases due to additional transistors
Solution Approach 1:
The patent applies segmentation by dividing the bit line system into local and global segments connected by transfer transistors. This segmentation reduces the total capacitance that needs to be driven at any one time while using the transistors as efficient connection points. The segmented architecture allows for better spatial utilization and reduced overall circuit area compared to a fully connected system.
Data Source
AI summary
A first write transistor has a source connected to a power-supply node, a drain connected to a first local bit line, and a gate connected to a second write global bit line. A second write transistor has a source connected to the power-supply node, a drain connected to a second local bit line, and a gate connected to a first write global bit line. A third write transistor has a source connected to the first write global bit line, a drain connected to the first local bit line, and a gate receiving a first control signal. A fourth write transistor has a source connected to the second write global bit line, a drain connected to the second local bit line, and a gate receiving the first control signal. A read circuit is connected to the first and second local bit lines and first and second read global bit lines.