Semiconductor Memory Device Bit Line Voltage Adjustment
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Solution Overview
Problem
Current semiconductor memory devices face challenges in efficiently managing contact resistances between semiconductor layers, which affect read operation accuracy due to variations in contact resistance across memory groups, leading to inconsistent data retrieval.
Innovation Solution
The semiconductor memory device employs a variable resistor module to adjust bit line voltages and sense time parameters, ensuring appropriate channel voltages across memory groups, thereby reducing the influence of contact resistance variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional semiconductor memory devices are used with fixed bit line voltages, then device structure is simple, but read operation accuracy deteriorates due to contact resistance variations across memory groups
Solution Approach 1:
The patent implements dynamic voltage adjustment by introducing a variable resistor module that changes bit line voltages based on memory group location. Different voltage levels (VBL0 to VBL3) are applied to different bit line groups during read operations, transforming the static voltage system into a dynamic one that adapts to contact resistance variations across the device.
Solution Approach 2:
The patent changes the voltage parameter of bit lines to compensate for contact resistance variations. By adjusting voltage levels across different bit line groups (with voltages ranging from lowest to highest in order B0 to B3), the system modifies electrical parameters to maintain consistent read operation accuracy despite variations in contact resistance across memory groups.
2Measurement precision
If uniform bit line voltages are applied to all memory groups, then device operation is simple, but read accuracy deteriorates due to inconsistent channel voltages across memory groups
Solution Approach 1:
The patent applies different voltage levels to different bit line groups based on their local characteristics. Memory groups are divided into four groups (MG0 to MG3) with progressively higher voltage levels (VBL0 to VBL3), allowing each local region to operate with optimized voltage that compensates for its specific contact resistance characteristics.
Solution Approach 2:
The system modifies the voltage parameter locally across different bit line groups to achieve consistent channel voltages. By changing voltage levels from lowest (VBL0) to highest (VBL3) across memory groups, the patent ensures that despite uniform structure, each local region experiences appropriate voltage conditions for accurate data retrieval.
3Measurement precision
If contact resistance variations are not compensated, then device structure remains simple, but read operation accuracy and data retrieval consistency deteriorate
Solution Approach 1:
The patent introduces a variable resistor module as an intermediary component between the bit lines and memory groups. This mediator adjusts voltage levels to compensate for contact resistance variations, acting as a buffer that transforms the simple but inaccurate direct connection into a controlled interface that maintains read accuracy.
Solution Approach 2:
The system changes electrical parameters (voltage levels) to compensate for contact resistance variations. By implementing four distinct voltage levels (VBL0 to VBL3) across different bit line groups, the patent modifies operational parameters to counteract the effects of contact resistance, thereby maintaining consistent read operation accuracy.
Data Source
AI summary
A semiconductor memory device includes a first conductive layer, a first and a second semiconductor layer opposed to the first conductive layer, a first and a second electric charge accumulating portion disposed between the first conductive layer and the first and the second semiconductor layer, and a first and a second bit line electrically connected to the first and the second semiconductor layer. A distance from a center position of the first conductive layer to the second semiconductor layer is smaller than a distance from the center position of the first conductive layer to the first semiconductor layer. When a read operation is executed on a first memory cell including the first electric charge accumulating portion and a second memory cell including the second electric charge accumulating portion, a voltage of the second bit line is larger than a voltage of the first bit line.