Semiconductor Memory Device Dynamic Bit Line Voltage Control

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Solution Overview

Problem

Existing NAND flash memory devices face challenges in efficiently managing the threshold voltage distribution during programming operations, leading to issues such as increased write performance variability and potential errors due to voltage margin limitations and coupling capacitance effects.

Innovation Solution

The implementation of a control circuit that dynamically adjusts the voltage applied to bit lines during programming, using a quick pass write system without relying on a dedicated QPW voltage, and optimizing the timing of voltage application to manage the electric potential difference between word lines and channels, thereby controlling the threshold voltage shift effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a dedicated QPW voltage is used for quick pass write operations, then write performance is improved, but device complexity increases due to additional voltage generation circuits

Engineering Contradiction:
Improvewrite performanceVSAvoidvoltage generation circuit complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The control circuit is designed to perform multiple functions: it generates both the program voltage (PGM) for normal programming operations and the quick pass write voltage (QPW) for fast programming operations. By integrating these voltage generation capabilities into a single control circuit, the patent eliminates the need for separate dedicated QPW voltage generation circuits, thereby improving write performance while avoiding increased device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Speed

If higher program voltages are applied to increase threshold voltage shift, then programming speed is improved, but voltage margin limitations are exceeded leading to errors

Engineering Contradiction:
Improveprogramming speedVSAvoidprogramming accuracy
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The control circuit dynamically adjusts the program voltage applied to the bit line based on the programming state and requirements. For quick pass write operations, it applies a higher program voltage (QPW) to achieve faster threshold voltage shift and improve programming speed. For normal operations, it applies a standard program voltage (PGM) to maintain voltage margins and ensure programming accuracy. This dynamic voltage adjustment allows the system to optimize programming speed without consistently exceeding voltage margin limitations.

Inventive Principle:
Principle #15Dynamics

3Productivity

If programming operations are performed faster, then productivity is improved, but threshold voltage distribution widens causing errors

Engineering Contradiction:
Improveprogramming throughputVSAvoidthreshold voltage distribution control
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The quick pass write function applies an excessive program voltage (higher than the standard PGM voltage) to achieve faster threshold voltage shift and improve programming throughput. However, this excessive voltage is applied selectively only when quick pass write is enabled and appropriate, not during all programming operations. By controlling the application of this excessive voltage through the control circuit's logic, the system achieves faster programming when needed while maintaining proper threshold voltage distribution control during normal operations, thus resolving the contradiction between productivity and manufacturing precision.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS10580501B2Semiconductor memory device
Publication Date: 2020.03.03 KIOXIA CORP
  • US10580501B2 patent drawing
  • US10580501B2 patent drawing
  • US10580501B2 patent drawing

AI summary

According to one embodiment, a semiconductor memory device includes a memory cell array having a plurality of memory cells, a plurality of bit lines, each bit line being connected to one of the memory cells in the plurality of memory cells, and a word line commonly connected to the plurality of memory cells. A control circuit is configured to apply a program voltage to the word line and to change a voltage applied to a first bit line in the plurality of bit lines within a first period in which the program voltage is being applied to the word line.