Semiconductor Memory Low-Data Holding Power Supply Control
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Solution Overview
Problem
Semiconductor memory with flip flop type memory cells faces challenges in achieving stable memory cell characteristics due to variations in transistor characteristics and decreased supply voltage, leading to decreased yield and static noise margin, particularly in 1-port and 2-port SRAMs where read and write operations are simultaneously performed.
Innovation Solution
The semiconductor memory employs a low-data holding power supply control circuit to control the potential of the low-data holding power supply, with each memory cell having two cross-coupled inverter circuits and a precharge circuit that precharges bit lines with a lower current, ensuring the potential of the low-data holding power supply for selected bit lines is higher than unselected bit lines, and the high-data holding power supply potential is set based on temperature and voltage conditions to optimize static noise margin and write level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the supply voltage is decreased to reduce power consumption, then power consumption is reduced, but memory cell characteristics become unstable and static noise margin deteriorates
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the power supply voltage to memory cells based on operational state. Specifically, it uses different voltage levels for read operations versus write operations, and adjusts the potential of power supply lines (such as VSSM1/VSSM2) connected to memory cells during different operational phases. This allows the system to maintain stable memory cell characteristics during critical operations while reducing overall power consumption.
Solution Approach 2:
The patent implements dynamics by making the power supply configuration adaptive and time-varying. The potential of power supply lines connected to memory cells is changed dynamically based on whether a read or write operation is being performed. For example, during write operations, the potential difference between VSSM1 and VSSM2 is adjusted to facilitate reliable data writing, while during read operations, the configuration is optimized for data reading. This dynamic adaptation resolves the contradiction between low power consumption and stable characteristics.
2Productivity
If the write level is increased to improve write speed, then write operation time is reduced, but static noise margin becomes small and erroneous writing occurs
Solution Approach 1:
The patent applies dynamics by adjusting the write level adaptively based on operational requirements. The potential of power supply lines connected to memory cells is dynamically modified during write operations to achieve the necessary write level for reliable data writing. Specifically, the patent adjusts the potential difference between VSSM1 and VSSM2 to control the write level, allowing fast writing while preventing erroneous writes through controlled potential adjustments.
Solution Approach 2:
The patent uses parameter changes by modifying the voltage potential of power supply lines during write operations. The potential of VSSM1 and VSSM2 is adjusted to achieve optimal write conditions - increasing the write level sufficiently to ensure fast writing completion, while controlling the adjustment to maintain adequate static noise margin and prevent erroneous writing in adjacent cells.
3Ease of operation
If the potential of low-data holding power supply for selected bit lines is increased to improve write level, then write operation is facilitated, but power consumption increases
Solution Approach 1:
The patent applies local quality by making the power supply potential adjustment localized to only those memory cells that are currently being accessed for write operations. The potential of low-data holding power supply lines (VSSM1/VSSM2) is modified only for selected bit lines and word lines that are active during a write operation, while other power supply lines maintain their normal potential levels. This localized adjustment facilitates write operations in the selected cells without causing unnecessary power consumption increases across the entire memory array.
Data Source
AI summary
In a semiconductor memory including word lines and bit lines arranged in a matrix and a plurality of memory cells provided at intersections of the word lines and the bit lines, a bit line precharge circuit is provided for controlling the potential of a low-data holding power supply coupled to memory cells provided on a corresponding one of the bit lines. In a write operation, the bit line precharge circuit controls the potential of a low-data holding power supply of a memory cell corresponding to a selected bit line to be higher than the potential of a low-data holding power supply of a memory cell corresponding to an unselected bit line.