Semiconductor Memory Device Bit Line Metal Structure
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Solution Overview
Problem
The increasing density of memory cells in DRAM devices and shrinking device dimensions in the peripheral region pose challenges in enhancing operation performance and reducing electrical resistance effectively.
Innovation Solution
A manufacturing method using a replacement metal gate process to form a bit line metal structure in the memory cell region and a metal gate structure in the peripheral region, concurrently filling trenches with a metal conductive layer to reduce electrical resistance and enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density is increased and device dimensions are shrunk in the peripheral region, then storage capacity is improved, but operation performance deteriorates and electrical resistance increases
Solution Approach 1:
The patent applies different material qualities to different regions: copper material is selectively formed in bit line trenches of the memory cell region to reduce electrical resistance, while peripheral regions use conventional metal gates. This local differentiation allows high-density memory cells to maintain low resistance without compromising peripheral device performance.
Solution Approach 2:
The manufacturing process segments the semiconductor substrate into distinct regions (memory cell region and peripheral region) with different metal filling strategies. Bit line trenches in the memory cell region are filled with copper material, while other regions follow conventional processes, allowing targeted optimization of electrical resistance where it matters most.
2Reliability
If bit line electrical resistance is reduced to improve memory cell operation, then peripheral device performance may be compromised due to process complexity
Solution Approach 1:
The patent merges the bit line formation process with the metal gate formation process by using the same replacement metal gate methodology for both. Copper material is deposited and patterned simultaneously for bit lines in the memory cell region, eliminating the need for separate copper filling processes and reducing overall manufacturing complexity.
Solution Approach 2:
The replacement metal gate process serves multiple functions: it forms both the metal gate structures in peripheral regions and the bit line structures in memory cell regions. This multi-functionality reduces process steps and simplifies manufacturing while achieving low resistance bit lines.
Data Source
AI summary
A manufacturing method of a semiconductor memory device includes the following steps. A contact hole is formed on a memory cell region of a semiconductor substrate and exposes a part of the semiconductor substrate. A dielectric layer is formed on the semiconductor substrate. A first trench penetrating the dielectric layer is formed on a memory cell region of the semiconductor substrate. A second trench penetrating the dielectric layer is formed on the peripheral region. A metal conductive layer is formed. The first trench and the second trench are filled with the metal conductive layer for forming a bit line metal structure in the first trench and a first metal gate structure in the second trench. A contact structure is formed in the contact hole, and the contact structure is located between the bit line metal structure and the semiconductor substrate.