3D Semiconductor Memory Device Power Routing via Bit Line Segmentation
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in stably providing operating voltages due to limited power transfer paths, which can lead to unreliable voltage delivery to peripheral circuit elements, especially when coupling pads in the bottom wiring layer restrict the number of power transfer paths.
Innovation Solution
The semiconductor memory device employs a three-dimensional structure where bit lines are cut over dummy blocks, creating spaces for power pads and coupling lines that allow for additional power transfer paths, ensuring stable voltage delivery by avoiding spatial limitations from coupling pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If coupling pads are placed in the bottom wiring layer, then electrical connection is achieved, but the number of power transfer paths is limited
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of power transfer paths to a three-dimensional structure by stacking multiple wiring layers. Power pads are distributed across different layers (first wiring layer, second wiring layer, etc.), creating vertical power transfer paths that bypass the spatial limitations of the bottom coupling pads. This multi-layer approach increases the number of available power transfer paths without increasing the footprint area.
2Reliability
If bit lines are continuous without cuts, then electrical continuity is maintained, but power transfer paths are blocked by coupling pads
Solution Approach 1:
The patent segments the bit lines by introducing cuts at specific locations where dummy blocks are positioned. These cuts divide continuous bit lines into separate sections, creating spaces that can accommodate power pads and coupling lines. The segmentation allows power transfer paths to be routed independently without being blocked by coupling pads, while the cut sections are electrically reconnected through vertical vias to maintain overall bit line continuity.
3Productivity
If operating voltage is provided through limited paths, then device operation is achieved, but voltage stability is compromised
Solution Approach 1:
The patent implements local quality by providing power through multiple distributed paths rather than a single uniform path. Different wiring layers and regions have specialized power transfer functions, with power pads strategically positioned to serve specific local areas. This distributed power delivery approach ensures that voltage drops and interference in one path do not affect the entire device, thereby improving voltage stability while maintaining full device operation.
Data Source
AI summary
A semiconductor memory device includes a memory chip defined with a first pad on one surface thereof; and a circuit chip defined with a second pad which is coupled with the first pad, on one surface thereof bonded with the one surface of the memory chip. The memory chip comprising: a memory cell array; a bit line disposed in a first wiring layer between the one surface and the memory cell array, and separated into a first bit line section and a second bit line section; and a power pad disposed in a space between the first bit line section and the second bit line section in the first wiring layer, and coupled with the first pad.