3D Stacked Semiconductor Memory Device With Bonded Wiring Layers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor memory devices with 3-dimensional structures do not adequately improve memory density per unit area due to limitations in the arrangement and connectivity of memory cell arrays.
Innovation Solution
The semiconductor memory device comprises two 3-dimensionally arrayed memory cell layers bonded together with facing wiring layers, allowing for increased memory density by stacking and connecting memory cell arrays without substrates, reducing chip area and wiring lengths, and eliminating the need for costly deep substrate etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell arrays are arranged in a single layer with conventional substrate structures, then manufacturing processes are established, but memory density per unit area is insufficient
Solution Approach 1:
The patent transitions from a single-layer planar arrangement to a three-dimensional stacked configuration by bonding multiple memory cell array layers together. Each layer is connected through bonding surfaces with facing wiring layers, enabling vertical stacking that dramatically increases memory density per unit area without requiring additional chip area.
Solution Approach 2:
The memory device is divided into multiple independent memory cell array layers that can be manufactured separately and then bonded together. Each layer functions as an independent memory cell array with its own wiring structure, allowing for modular assembly and increased overall capacity through stacking.
2Quantity of substance
If multiple memory cell arrays are stacked with substrate structures, then memory capacity increases, but deep substrate etching processes are required which increase manufacturing complexity and cost
Solution Approach 1:
The patent removes the substrate from the conventional structure and replaces it with bonding surfaces between memory cell array layers. This extraction eliminates the need for deep substrate etching processes while still enabling multiple layers to be stacked and connected through facing wiring layers bonded at their interfaces.
Solution Approach 2:
Instead of etching deep holes through substrates to connect layers from below, the patent inverts the connection approach by bonding layers together at their facing surfaces with wiring layers that connect vertically through the stack. This reverses the conventional etching-from-substrate approach to a bonding-from-surface approach.
3Quantity of substance
If conventional single-layer memory structures are used, then wiring lengths are minimized, but memory density per unit area cannot be sufficiently improved
Solution Approach 1:
The patent resolves the wiring length issue by transitioning to vertical stacking in the third dimension. Facing wiring layers in adjacent layers are bonded together at their interfaces, creating short vertical connections that minimize wiring length while enabling multiple memory layers to be stacked for increased density.
Data Source
AI summary
A semiconductor memory device includes a first memory cell array layer includes a first memory cell array region, in which memory cells are 3-dimensionally arrayed, and a first and second surface wiring layer connected to the memory cells. A second memory cell array layer includes second memory cell array region, in which memory cells are 3-dimensionally arrayed, and a third and fourth surface wiring layer connected to the second plurality of memory cells. The first memory cell array layer and the second memory cell array layer are bonded to each other such that the second surface wiring layer and the third surface wiring layer face each other and are bonded to each other. The first and second memory cell array regions overlap each other as viewed from a direction orthogonal to a layer plane.