Semiconductor Memory Device Buffer Layer Residue Prevention

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Solution Overview

Problem

The integration of semiconductor devices is hindered by the formation of conductive residues between the cell array and peripheral circuit regions, leading to electrical shorts and reduced reliability.

Innovation Solution

A method involving the formation of a semiconductor memory device where a semiconductor layer with a different lattice constant is grown on the peripheral circuit region, and a buffer layer is used to cover the cell array region, preventing the formation of conductive residues by ensuring complete removal of mask patterns and proper filling of recess regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If mask patterns are used to cover the cell array region and expose the peripheral circuit region, then selective growth of semiconductor layer is achieved, but conductive residues may form between regions causing electrical shorts

Engineering Contradiction:
Improvepatterning accuracyVSAvoidelectrical short prevention
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

A buffer layer is introduced as an intermediary between the cell array region and peripheral circuit region. This buffer layer prevents direct contact between conductive materials from the two regions, eliminating the harmful effect of conductive residues causing electrical shorts while allowing the mask pattern to continue serving its patterning function.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The structure is segmented into distinct regions: cell array region, buffer layer, and peripheral circuit region. This segmentation creates physical separation that prevents conductive residue formation between regions, while maintaining the selective growth capability provided by the mask pattern.

Inventive Principle:
Principle #1Segmentation

2Productivity

If integration density is increased by reducing pattern widths, then more devices fit on chip, but complete removal of mask patterns becomes more difficult leading to conductive residue formation

Engineering Contradiction:
Improveintegration densityVSAvoidmask pattern removal
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

The buffer layer serves as a mediator that allows mask patterns to be placed close together for high integration density while preventing the harmful interaction between adjacent mask patterns. Even if mask patterns are not completely removed, the buffer layer prevents conductive residue formation.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The potential harm of incomplete mask pattern removal at high integration densities is converted into a benefit by introducing the buffer layer. The buffer layer accepts the presence of residual mask material and prevents it from causing electrical shorts, thereby enabling higher integration densities without compromising reliability.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances the reliability of semiconductor memory devices by preventing electrical shorts and improving integration density by ensuring accurate patterning and isolation between regions.

Implementation Method 1

growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate

Methodology Applied
Scientific EffectEpitaxial growth: Epitaxy

Data Source

PatentUS11521977B2Semiconductor memory device
Publication Date: 2022.12.06 SAMSUNG ELECTRONICS CO LTD
  • US11521977B2 patent drawing
  • US11521977B2 patent drawing
  • US11521977B2 patent drawing

AI summary

A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.