Semiconductor Memory Data Buffering Parallel Write Control
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Solution Overview
Problem
Semiconductor memory devices face challenges in achieving both high read and write performance, particularly in nonvolatile memory systems where existing technologies struggle to optimize data transfer and storage efficiency.
Innovation Solution
A semiconductor memory device with a controller that manages data transfer to multiple nonvolatile semiconductor memories in parallel, utilizing a buffer to temporarily store data from a host and employing different write methods (vertical, 9-channel return, and horizontal writes) based on data reception situations to improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is written sequentially to multiple nonvolatile semiconductor memories, then write performance is improved, but read performance deteriorates due to sequential access limitations
Solution Approach 1:
The patent divides the write operation into multiple independent parallel channels (first nonvolatile semiconductor memory and second nonvolatile semiconductor memory). Each channel can independently write data to its target memory simultaneously, transforming a sequential write process into parallel operations. This segmentation allows both write and read operations to benefit from concurrent access across multiple memory devices.
2Adaptability or versatility
If a buffer is used to temporarily store data, then data transfer flexibility is improved, but buffer depletion occurs under high write loads
Solution Approach 1:
The patent extends the buffer capacity by introducing a second nonvolatile semiconductor memory that functions as an extended buffer region. When the primary buffer becomes full, data can be transferred to the second memory's buffer, effectively creating a multi-dimensional storage hierarchy. This dimensional expansion allows the system to handle high write loads without depleting the primary buffer, while maintaining data transfer flexibility through multiple storage destinations.
3Productivity
If parallel write operations are implemented across multiple memories, then overall write performance is improved, but system complexity increases
Solution Approach 1:
The patent merges the control logic for multiple memory devices into a unified controller that manages both nonvolatile semiconductor memories through standardized interfaces. By combining the control functions and using identical memory device structures, the system achieves parallel write performance while minimizing the increase in complexity through modular, replicated components rather than fundamentally different architectures.
Data Source
AI summary
A semiconductor storage device includes at least two nonvolatile semiconductor memories, a buffer in which data received from a host and to be written to the nonvolatile semiconductor memories in response to a write command received from the host can be temporarily stored, and a controller connected to the nonvolatile semiconductor memories and configured to transfer data stored in the buffer to a number N of the nonvolatile semiconductor memories in parallel. The number N is set according to a reception of data from the host, and N is greater than or equal to 1 and less than or equal to m, which is the number of nonvolatile semiconductor memories connected to the controller.