Semiconductor Memory Bypass Via Linear Shape
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional two-dimensional semiconductor memory devices face limitations in increasing integration density due to the need for expensive equipment for miniaturization, and there is a challenge in preventing arching during the formation of channel holes, which affects the arrangement of peripheral transistors, lower wiring structures, and upper wires.
Innovation Solution
A semiconductor memory device with a peripheral logic structure and a cell array structure are stacked, where bypass vias electrically connect the cell substrate and the peripheral logic substrate, allowing for a linear shape extending in specific directions to prevent arching and provide sufficient space for transistors and wiring structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional two-dimensional planar semiconductor memory device structure is used, then manufacturing process is simpler, but integration density cannot be increased sufficiently
Solution Approach 1:
The patent transitions from a conventional two-dimensional planar structure to a three-dimensional stacked structure. The cell array structure is formed on top of the peripheral logic structure, utilizing the vertical dimension to increase integration density. This dimensional change allows memory cells to be arranged in multiple layers, significantly increasing the number of storage elements per unit area without requiring further miniaturization of individual components.
2Reliability
If bypass vias are formed with conventional shapes, then electrical connection is achieved, but arching occurs affecting peripheral transistor arrangement
Solution Approach 1:
The patent changes the geometric parameters of the bypass via by forming it with a linear shape extending in first and second directions that are parallel to the upper surface of the cell substrate. This linear configuration, as opposed to conventional vertical or angled via shapes, prevents the accumulation of stress that causes arching during the formation of channel holes, while still maintaining effective electrical connection between the cell substrate and peripheral logic substrate.
3Ease of operation
If more space is allocated for peripheral transistors and wiring, then device functionality is improved, but integration density decreases
Solution Approach 1:
The patent resolves this contradiction by moving peripheral transistors and wiring structures from the planar area to the vertical dimension through the stacked configuration. The peripheral logic structure with its transistors and wiring is formed on top of the cell array structure, allowing both the cell array and peripheral circuits to coexist in three-dimensional space. This enables sufficient space for peripheral components without sacrificing integration density, as the footprint on the substrate remains compact.
Data Source
AI summary
A semiconductor memory device has a peripheral logic structure including a peripheral logic substrate and a peripheral logic insulating film on the peripheral logic substrate. A cell array structure includes a cell substrate and a source structure that are sequentially stacked on the peripheral logic structure. A bypass via electrically connects the cell substrate and the peripheral logic substrate. The bypass via has a linear shape extending in at least one of first and second directions on the cell substrate. The first and second directions are parallel to an upper surface of the cell substrate.