Semiconductor Memory Write Reliability via Capacitive Coupling
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in ensuring the reliability of write operations, particularly due to potential erroneous writing caused by drops in power supply voltage, which can lead to increased channel potential differences and incorrect data storage.
Innovation Solution
The semiconductor memory device employs a method where the potential of a bit line, source line, and select gate line of a non-selected block are increased through capacitive coupling, allowing the boosted voltage to be trapped in the channel, ensuring that the channel potential remains higher than the power supply voltage during write operations, thus preventing erroneous writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If charge pumps are added to maintain channel potential during write operations, then write reliability is improved, but current consumption and chip area increase
Solution Approach 1:
The patent extracts and eliminates the charge pump component from the system by using an alternative approach. Instead of adding active voltage boosting circuitry, the invention uses carefully timed voltage applications to select gate lines and bit lines that passively maintain channel potential above power supply voltage during write operations, thereby removing the need for charge pumps and their associated current consumption and chip area
Solution Approach 2:
The patent applies preliminary voltage to select gate lines and bit lines before the actual write operation to pre-charge the channel and ensure the channel potential remains above the power supply voltage. This preliminary action prevents voltage drops during writing without requiring active charge pumping during the critical write phase
2Reliability
If charge pumps are added to maintain channel potential during write operations, then write reliability is improved, but chip area increases
Solution Approach 1:
The patent extracts and eliminates the charge pump component from the system by using an alternative approach. Instead of adding active voltage boosting circuitry, the invention uses carefully timed voltage applications to select gate lines and bit lines that passively maintain channel potential above power supply voltage during write operations, thereby removing the need for charge pumps and their associated chip area
Solution Approach 2:
The patent makes existing circuit elements (select gate lines, bit lines, and transistor channels) perform the additional function of voltage maintenance. These components already exist for other purposes, but the patent exploits their capacitive coupling and voltage storage capability to maintain channel potential, eliminating the need for dedicated charge pump circuitry
3Use of energy by moving object
If power supply voltage is reduced to save energy, then energy consumption is decreased, but channel potential drops and erroneous writing occurs
Solution Approach 1:
The patent applies preliminary voltage to select gate lines and bit lines before the actual write operation to pre-charge the channel and ensure the channel potential remains above the power supply voltage. This preliminary action prevents voltage drops during writing without requiring active charge pumping during the critical write phase
Solution Approach 2:
The patent enables the memory cell channel to maintain its own potential above the power supply voltage through capacitive coupling with externally controlled lines. The channel essentially services itself by storing charge and maintaining potential without requiring external charge pump assistance, allowing low power supply operation while preventing erroneous writing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of write operations by maintaining sufficient channel potential and preventing erroneous writing, even at lower power supply voltages, without the need for additional charge pumps, thereby reducing current consumption and chip area.
Implementation Method 1
the potential of a bit line, source line, and select gate line of a non-selected block are increased through capacitive coupling, allowing the boosted voltage to be trapped in the channel
Data Source
AI summary
A semiconductor memory device includes a first memory block having a first memory cell transistor and a first select transistor, a second memory block having a second memory cell transistor and a second select transistor, a first select gate line that is electrically connected to a gate of the first select transistor, and a second select gate line that is electrically connected to a gate of the second select transistor. During writing of data to a memory cell transistor in the first block, a first voltage is applied to the first select gate line during a first time period, a second voltage is applied to the second select gate line during a second time period after the first time period, and a third voltage lower than the first voltage is applied to the first select gate line during a third time period after the second time period.