Semiconductor Memory Device Vertical Capacitor Stacking
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Solution Overview
Problem
The challenge in semiconductor memory devices is to achieve high integration and reliability while overcoming the physical scaling limits of two-dimensional nonvolatile memory devices, particularly in efficiently utilizing chip space and reducing device size.
Innovation Solution
A semiconductor memory device is designed with a capacitor formed in a fine pattern within a dummy area, utilizing a lower and upper bonding layer structure to couple capacitor structures, allowing for vertical stacking and efficient use of space, thereby enhancing integration and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If two-dimensional nonvolatile memory device structure is used, then manufacturing process is simple, but integration density is limited due to physical scaling limits
Solution Approach 1:
The patent transitions from a two-dimensional memory structure to a three-dimensional structure by vertically stacking multiple bonding layers (lower bonding layer, intermediate bonding layer, upper bonding layer) and forming capacitor structures in both planar and vertical orientations. This dimensional change enables higher integration density by utilizing the vertical space above the substrate, effectively overcoming the physical scaling limits of conventional 2D architectures.
Solution Approach 2:
The patent implements nested capacitor structures where upper capacitor structures are positioned directly above lower capacitor structures, forming a vertically integrated capacitive system. The intermediate bonding layer is nested between the lower and upper bonding layers, creating a compact multi-layer configuration that maximizes space utilization and enhances integration density without proportionally increasing device footprint.
2Quantity of substance
If chip area is increased to accommodate more circuits, then integration capacity increases, but device size and cost increase
Solution Approach 1:
The patent employs vertical stacking of bonding layers and capacitor structures to increase the number of circuits and capacitors without proportionally increasing the chip area. By utilizing the third dimension (vertical direction), the device accommodates more functional elements within a limited planar footprint, effectively decoupling circuit quantity from area expansion.
Solution Approach 2:
The patent combines multiple functions into integrated structures: the bonding layers serve both as structural interconnects and as platforms for capacitor formation; the dummy area is merged with functional areas to form a unified capacitor array; and peripheral circuit components are integrated with memory cell structures. This merging reduces the total chip area required by eliminating redundant spaces and shared structures.
3Area of stationary object
If capacitor structures are formed in dummy area, then space utilization improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies different capacitor formation approaches in different regions: in the dummy area, capacitor structures are formed using the same materials and processes as in functional areas, ensuring uniform quality. The intermediate bonding layer is selectively positioned to provide local structural support where needed, while maintaining overall manufacturing consistency across the entire chip surface.
Solution Approach 2:
The patent utilizes parameter changes in the capacitor structures, such as varying the thickness of bonding layers or the dimensions of capacitor electrodes in different regions, to optimize both space utilization and manufacturing precision. By adjusting these parameters locally, the design accommodates the specific requirements of dummy areas while maintaining compatibility with standard manufacturing processes.
Data Source
AI summary
Provided herein are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a lower substrate, a peripheral circuit component located on the lower substrate, a lower bonding layer including a lower capacitor structure, the capacitor structure located on the peripheral circuit component, an upper bonding layer including an upper capacitor structure, the upper bonding layer bonded to the lower bonding layer, a plurality of cells and a dummy insulating layer that are located on the upper bonding layer, and an upper substrate being located on the plurality of cells and the dummy insulating layer, wherein the upper capacitor structure is coupled to the lower capacitor structure.